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/src/contrib/llvm-project/clang/include/clang/Basic/
H A DStmtNodes.td9 def Stmt : StmtNode<?, 1>;
10 def NullStmt : StmtNode<Stmt>;
11 def CompoundStmt : StmtNode<Stmt>;
12 def IfStmt : StmtNode<Stmt>;
13 def SwitchStmt : StmtNode<Stmt>;
14 def WhileStmt : StmtNode<Stmt>;
15 def DoStmt : StmtNode<Stmt>;
16 def ForStmt : StmtNode<Stmt>;
17 def GotoStmt : StmtNode<Stmt>;
18 def IndirectGotoStmt : StmtNode<Stmt>;
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H A DDeclNodes.td12 def Decl : DeclNode<?, "", 1>;
13 def TranslationUnit : DeclNode<Decl>, DeclContext;
14 def PragmaComment : DeclNode<Decl>;
15 def PragmaDetectMismatch : DeclNode<Decl>;
16 def ExternCContext : DeclNode<Decl>, DeclContext;
17 def Named : DeclNode<Decl, "named declarations", 1>;
18 def Namespace : DeclNode<Named, "namespaces">, DeclContext;
19 def UsingDirective : DeclNode<Named>;
20 def NamespaceAlias : DeclNode<Named>;
21 def Label : DeclNode<Named, "labels">;
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H A DDiagnosticGroups.td9 def ImplicitFunctionDeclare : DiagGroup<"implicit-function-declaration">;
10 def ImplicitInt : DiagGroup<"implicit-int">;
13 def Implicit : DiagGroup<"implicit", [
19 def ODR : DiagGroup<"odr">;
20 def : DiagGroup<"abi">;
21 def : DiagGroup<"gnu-empty-initializer">; // Now a C extension, not GNU.
22 def AbsoluteValue : DiagGroup<"absolute-value">;
23 def MisspelledAssumption : DiagGroup<"misspelled-assumption">;
24 def UnknownAssumption : DiagGroup<"unknown-assumption">;
25 def AddressOfTemporary : DiagGroup<"address-of-temporary">;
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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedule.td9 /// Define scheduler resources associated with def operands.
10 def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations
11 def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I
12 def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations
13 def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
14 def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations
15 def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix
16 def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide
17 def WriteIDiv32 : SchedWrite; // 32-bit divide on RV64I
18 def WriteIRem : SchedWrite; // 32-bit or 64-bit remainder
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H A DRISCVSchedSiFiveP400.td11 def SiFiveP400Model : SchedMachineModel {
30 def SiFiveP400IEXQ0 : ProcResource<1>;
31 def SiFiveP400IEXQ1 : ProcResource<1>;
32 def SiFiveP400IEXQ2 : ProcResource<1>;
33 def SiFiveP400FEXQ0 : ProcResource<1>;
34 def SiFiveP400Load : ProcResource<1>;
35 def SiFiveP400Store : ProcResource<1>;
37 def SiFiveP400IntArith : ProcResGroup<[SiFiveP400IEXQ0, SiFiveP400IEXQ1, SiFiveP400IEXQ2]>;
42 def SiFiveP400Div : ProcResource<1>;
46 def SiFiveP400FloatDiv : ProcResource<1>;
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H A DRISCVSchedXiangShanNanHu.td19 def XiangShanNanHuModel : SchedMachineModel {
34 def XS2ALU : ProcResource<4>;
35 def XS2MDU : ProcResource<2>;
36 def XS2MISC : ProcResource<1>;
38 def XS2FMAC : ProcResource<4>;
39 def XS2FMISC : ProcResource<2>;
42 def XS2LD : ProcResource<2>;
43 def XS2ST : ProcResource<2>;
47 def : WriteRes<WriteJmp, [XS2MISC]>;
48 def : WriteRes<WriteJal, [XS2MISC]>;
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H A DRISCVScheduleZb.td9 /// Define scheduler resources associated with def operands.
12 def WriteSHXADD : SchedWrite; // sh1add/sh2add/sh3add
13 def WriteSHXADD32 : SchedWrite; // sh1add.uw/sh2add.uw/sh3add.uw
16 def WriteRotateImm : SchedWrite;
17 def WriteRotateImm32 : SchedWrite;
18 def WriteRotateReg : SchedWrite;
19 def WriteRotateReg32 : SchedWrite;
20 def WriteCLZ : SchedWrite;
21 def WriteCLZ32 : SchedWrite;
22 def WriteCTZ : SchedWrite;
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H A DRISCVSchedRocket.td14 def RocketModel : SchedMachineModel {
33 def RocketUnitALU : ProcResource<1>; // Int ALU
34 def RocketUnitIMul : ProcResource<1>; // Int Multiply
35 def RocketUnitMem : ProcResource<1>; // Load/Store
36 def RocketUnitB : ProcResource<1>; // Branch
38 def RocketUnitFPALU : ProcResource<1>; // FP ALU
42 def RocketUnitIDiv : ProcResource<1>; // Int Division
43 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
51 def : WriteRes<WriteJmp, [RocketUnitB]>;
52 def : WriteRes<WriteJal, [RocketUnitB]>;
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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrInfo.td19 def MOVGR2SCR : FmtGR2SCR<0x00000800>;
20 def MOVSCR2GR : FmtSCR2GR<0x00000c00>;
22 def JISCR0 : FmtJISCR<0x48000200>;
23 def JISCR1 : FmtJISCR<0x48000300>;
25 def ADDU12I_W : ALU_2RI5<0x00290000, simm5>;
27 def ADC_B : ALU_3R<0x00300000>;
28 def ADC_H : ALU_3R<0x00308000>;
29 def ADC_W : ALU_3R<0x00310000>;
31 def SBC_B : ALU_3R<0x00320000>;
32 def SBC_H : ALU_3R<0x00328000>;
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/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsHexagonDep.td1063 def int_hexagon_A2_abs :
1066 def int_hexagon_A2_absp :
1069 def int_hexagon_A2_abssat :
1072 def int_hexagon_A2_add :
1075 def int_hexagon_A2_addh_h16_hh :
1078 def int_hexagon_A2_addh_h16_hl :
1081 def int_hexagon_A2_addh_h16_lh :
1084 def int_hexagon_A2_addh_h16_ll :
1087 def int_hexagon_A2_addh_h16_sat_hh :
1090 def int_hexagon_A2_addh_h16_sat_hl :
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H A DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
17 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty],
19 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
21 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty],
24 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
26 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty],
28 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
31 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
35 def int_aarch64_clrex : Intrinsic<[]>;
37 def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/src/contrib/llvm-project/clang/include/clang/AST/
H A DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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H A DCommentCommands.td53 def Begin : Command<name> {
58 def End : Command<endCommandName> {
91 def B : InlineCommand<"b">;
92 def C : InlineCommand<"c">;
93 def P : InlineCommand<"p">;
94 def A : InlineCommand<"a">;
95 def E : InlineCommand<"e">;
96 def N : InlineCommand<"n"> { let NumArgs = 0; }
97 def Em : InlineCommand<"em">;
98 def Emoji : InlineCommand<"emoji">;
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUSearchableTables.td19 def RsrcIntrinsics : GenericTable {
30 def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
51 def Gfx9BufferFormat : GcnBufferFormatTable {
55 def Gfx10BufferFormat : GcnBufferFormatTable {
59 def Gfx11PlusBufferFormat : GcnBufferFormatTable {
64 def getGfx9BufferFormatInfo : SearchIndex {
68 def getGfx10BufferFormatInfo : SearchIndex {
72 def getGfx11PlusBufferFormatInfo : SearchIndex {
78 def : Gfx9BufferFormat< /*FORMAT_8_UNORM*/ 0x01, 8, 1, /*NUM_FORMAT_UNORM*/ 0, /*DA…
79 def : Gfx9BufferFormat< /*FORMAT_8_SNORM*/ 0x11, 8, 1, /*NUM_FORMAT_SNORM*/ 1, /*DA…
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H A DSISchedule.td13 def : PredicateProlog<[{
19 def WriteBranch : SchedWrite;
20 def WriteExport : SchedWrite;
21 def WriteLDS : SchedWrite;
22 def WriteSALU : SchedWrite;
23 def WriteSMEM : SchedWrite;
24 def WriteVMEM : SchedWrite;
25 def WriteBarrier : SchedWrite;
27 def MIVGPRRead : SchedRead;
28 def MIMFMARead : SchedRead;
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/src/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DDXIL.td26 def acceptHitAndEndSearch : DXILOpClass;
27 def allocateNodeOutputRecords : DXILOpClass;
28 def allocateRayQuery : DXILOpClass;
29 def annotateHandle : DXILOpClass;
30 def annotateNodeHandle : DXILOpClass;
31 def annotateNodeRecordHandle : DXILOpClass;
32 def atomicBinOp : DXILOpClass;
33 def atomicCompareExchange : DXILOpClass;
34 def attributeAtVertex : DXILOpClass;
35 def barrier : DXILOpClass;
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/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRDevices.td34 def FeatureSRAM : SubtargetFeature<"sram", "HasSRAM", "true",
38 def FeatureJMPCALL : SubtargetFeature<"jmpcall", "HasJMPCALL", "true",
43 def FeatureIJMPCALL : SubtargetFeature<"ijmpcall", "HasSRAMIJMPCALL", "true",
48 def FeatureEIJMPCALL : SubtargetFeature<"eijmpcall", "HasEIJMPCALL", "true",
53 def FeatureADDSUBIW : SubtargetFeature<"addsubiw", "HasADDSUBIW", "true",
58 def FeatureSmallStack
64 def FeatureMOVW : SubtargetFeature<"movw", "HasMOVW", "true",
69 def FeatureLPM : SubtargetFeature<"lpm", "HasLPM", "true",
73 def FeatureLPMX : SubtargetFeature<"lpmx", "HasLPMX", "true",
78 def FeatureELPM : SubtargetFeature<"elpm", "HasELPM", "true",
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/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSchedule.td12 def ALU : FuncUnit;
13 def IMULDIV : FuncUnit;
19 def IIM16Alu : InstrItinClass;
20 def IIPseudo : InstrItinClass;
22 def II_ABS : InstrItinClass;
23 def II_ADDI : InstrItinClass;
24 def II_ADDIU : InstrItinClass;
25 def II_ADDIUPC : InstrItinClass;
26 def II_ADD : InstrItinClass;
27 def II_ADDU : InstrItinClass;
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H A DMipsScheduleGeneric.td16 def MipsGenericModel : SchedMachineModel {
39 def GenericALU : ProcResource<1> { let BufferSize = 1; }
40 def GenericIssueALU : ProcResource<1> { let Super = GenericALU; }
42 def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>;
47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
53 def : InstRW<[GenericWriteALU], (instrs COPY)>;
59 def : InstRW<[GenericWriteALU], (instrs ADDIUPC, ALIGN, ALUIPC, AUI,
66 def : InstRW<[GenericWriteALU], (instrs AddiuRxImmX16, AddiuRxRxImm16,
82 def : InstRW<[GenericWriteALU], (instrs Constant32, LwConstant32,
88 def : InstRW<[GenericWriteALU], (instrs ADDIUPC_MM, ADDIUR1SP_MM, ADDIUR2_MM,
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/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
33 def RegNamesStateReg : RegAltNameIndex;
64 def ICC : SparcCtrlReg<0, "icc">; // This represents icc and xcc in 64-bit code.
66 def FCC#I : SparcCtrlReg<I, "fcc"#I>;
68 def FSR : SparcCtrlReg<0, "fsr">; // Floating-point state register.
69 def FQ : SparcCtrlReg<0, "fq">; // Floating-point deferred-trap queue.
70 def CPSR : SparcCtrlReg<0, "csr">; // Co-processor state register.
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/src/contrib/llvm-project/clang/lib/AST/Interp/
H A DOpcodes.td19 def Bool : Type;
20 def Sint8 : Type;
21 def Uint8 : Type;
22 def Sint16 : Type;
23 def Uint16 : Type;
24 def Sint32 : Type;
25 def Uint32 : Type;
26 def Sint64 : Type;
27 def Uint64 : Type;
28 def IntAP : Type;
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/src/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td49 def : GINodeEquiv<G_ANYEXT, anyext>;
50 def : GINodeEquiv<G_SEXT, sext>;
51 def : GINodeEquiv<G_ZEXT, zext>;
52 def : GINodeEquiv<G_TRUNC, trunc>;
53 def : GINodeEquiv<G_BITCAST, bitconvert>;
56 def : GINodeEquiv<G_CONSTANT, imm>;
58 def : GINodeEquiv<G_FCONSTANT, fpimm>;
59 def : GINodeEquiv<G_IMPLICIT_DEF, undef>;
60 def : GINodeEquiv<G_FRAME_INDEX, frameindex>;
61 def : GINodeEquiv<G_BLOCK_ADDR, blockaddress>;
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