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Searched refs:ctrl_register (Results 1 – 6 of 6) sorted by relevance

/src/sys/dev/sound/pci/
H A Dhdsp.c265 control = sc->ctrl_register & HDSP_INPUT_LEVEL_MASK; in hdsp_sysctl_input_level()
288 if (control != (sc->ctrl_register & HDSP_INPUT_LEVEL_MASK)) { in hdsp_sysctl_input_level()
290 sc->ctrl_register &= ~HDSP_INPUT_LEVEL_MASK; in hdsp_sysctl_input_level()
291 sc->ctrl_register |= control; in hdsp_sysctl_input_level()
292 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); in hdsp_sysctl_input_level()
329 control = sc->ctrl_register & HDSP_OUTPUT_LEVEL_MASK; in hdsp_sysctl_output_level()
352 if (control != (sc->ctrl_register & HDSP_OUTPUT_LEVEL_MASK)) { in hdsp_sysctl_output_level()
354 sc->ctrl_register &= ~HDSP_OUTPUT_LEVEL_MASK; in hdsp_sysctl_output_level()
355 sc->ctrl_register |= control; in hdsp_sysctl_output_level()
356 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); in hdsp_sysctl_output_level()
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H A Dhdspe-pcm.c429 sc->ctrl_register |= (HDSPE_AUDIO_INT_ENABLE | HDSPE_ENABLE); in hdspe_start_audio()
430 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); in hdspe_start_audio()
440 sc->ctrl_register &= ~(HDSPE_AUDIO_INT_ENABLE | HDSPE_ENABLE); in hdspe_stop_audio()
441 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); in hdspe_stop_audio()
876 sc->ctrl_register &= ~HDSPE_FREQ_MASK; in hdspechan_setspeed()
877 sc->ctrl_register |= hr->reg; in hdspechan_setspeed()
878 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); in hdspechan_setspeed()
946 sc->ctrl_register &= ~HDSPE_LAT_MASK; in hdspechan_setblocksize()
947 sc->ctrl_register |= hdspe_encode_latency(hl->n); in hdspechan_setblocksize()
948 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); in hdspechan_setblocksize()
H A Dhdsp-pcm.c443 sc->ctrl_register |= (HDSP_AUDIO_INT_ENABLE | HDSP_ENABLE); in hdsp_start_audio()
444 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); in hdsp_start_audio()
454 sc->ctrl_register &= ~(HDSP_AUDIO_INT_ENABLE | HDSP_ENABLE); in hdsp_stop_audio()
455 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); in hdsp_stop_audio()
886 sc->ctrl_register &= ~HDSP_FREQ_MASK; in hdspchan_setspeed()
887 sc->ctrl_register |= hr->reg; in hdspchan_setspeed()
888 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); in hdspchan_setspeed()
951 sc->ctrl_register &= ~HDSP_LAT_MASK; in hdspchan_setblocksize()
952 sc->ctrl_register |= hdsp_encode_latency(hl->n); in hdspchan_setblocksize()
953 hdsp_write_4(sc, HDSP_CONTROL_REG, sc->ctrl_register); in hdspchan_setblocksize()
H A Dhdspe.c700 sc->ctrl_register = hdspe_encode_latency(7); in hdspe_init()
705 sc->ctrl_register &= ~HDSPE_FREQ_MASK; in hdspe_init()
706 sc->ctrl_register |= HDSPE_FREQ_MASK_DEFAULT; in hdspe_init()
707 hdspe_write_4(sc, HDSPE_CONTROL_REG, sc->ctrl_register); in hdspe_init()
H A Dhdspe.h219 uint32_t ctrl_register; member
H A Dhdsp.h228 uint32_t ctrl_register; member