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Searched refs:createRegister (Results 1 – 16 of 16) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.cpp158 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
159 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
160 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
164 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
165 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
168 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
169 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
170 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
171 AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15); in fixedABILayout()
174 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask); in fixedABILayout()
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H A DSIMachineFunctionInfo.cpp79 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
95 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
153 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
193 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
200 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
207 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
215 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
222 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
229 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
236 ArgInfo.PrivateSegmentSize = ArgDescriptor::createRegister(getNextUserSGPR()); in addPrivateSegmentSize()
[all …]
H A DSIMachineFunctionInfo.h772 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
778 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
784 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
790 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
812 = ArgDescriptor::createRegister(getNextSystemSGPR());
818 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
H A DAMDGPUArgumentUsageInfo.h45 static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) {
H A DAMDGPUTargetMachine.cpp1634 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
H A DSIISelLowering.cpp2142 ArgDescriptor::createRegister(AMDGPU::TTMP9); in getPreloadedValue()
2146 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in getPreloadedValue()
2150 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in getPreloadedValue()
2255 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
2261 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2268 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
2275 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2282 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
2312 return ArgDescriptor::createRegister(Reg, Mask); in allocateVGPR32Input()
2329 return ArgDescriptor::createRegister(Reg); in allocateSGPR32InputImpl()
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H A DAMDGPULegalizerInfo.cpp4302 ArgDescriptor::createRegister(AMDGPU::TTMP9); in loadInputValue()
4306 const ArgDescriptor WorkGroupIDY = ArgDescriptor::createRegister( in loadInputValue()
4310 ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); in loadInputValue()
/src/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp105 DwarfRegs.push_back(Register::createRegister(-1, nullptr)); in addMachineReg()
115 DwarfRegs.push_back(Register::createRegister(Reg, nullptr)); in addMachineReg()
127 DwarfRegs.push_back(Register::createRegister(Reg, "super-register")); in addMachineReg()
167 DwarfRegs.push_back(Register::createRegister(Reg, "sub-register")); in addMachineReg()
H A DDwarfExpression.h53 static Register createRegister(int RegNo, const char *Comment) { in createRegister() function
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DCFIInstrInserter.cpp378 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp168 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA)); in emitPrologue()
/src/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCDwarf.h615 static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1,
/src/contrib/llvm-project/llvm/lib/MC/
H A DMCStreamer.cpp659 MCCFIInstruction::createRegister(Label, Register1, Register2, Loc); in emitCFIRegister()
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp1213 unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister( in emitPrologue()
/src/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp2566 MF.addFrameInst(MCCFIInstruction::createRegister(nullptr, Reg, Reg2)); in parseCFIOperand()
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp6502 MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg)); in emitCFIForLRSaveToReg()