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/src/contrib/unbound/dnstap/
H A Ddnstap_fstrm.c51 uint32_t* control; in fstrm_create_control_frame_start() local
62 control = malloc(n); in fstrm_create_control_frame_start()
63 if(!control) in fstrm_create_control_frame_start()
65 control[0] = 0; in fstrm_create_control_frame_start()
66 control[1] = htonl(4+4+4+strlen(contenttype)); in fstrm_create_control_frame_start()
67 control[2] = htonl(FSTRM_CONTROL_FRAME_START); in fstrm_create_control_frame_start()
68 control[3] = htonl(FSTRM_CONTROL_FIELD_TYPE_CONTENT_TYPE); in fstrm_create_control_frame_start()
69 control[4] = htonl(strlen(contenttype)); in fstrm_create_control_frame_start()
70 memmove(&control[5], contenttype, strlen(contenttype)); in fstrm_create_control_frame_start()
72 return control; in fstrm_create_control_frame_start()
[all …]
/src/sys/netinet/
H A Dsctp_indata.c62 sctp_add_chk_to_control(struct sctp_queued_to_read *control,
329 struct sctp_queued_to_read *control) in sctp_place_control_in_stream() argument
335 flags = (control->sinfo_flags >> 8); in sctp_place_control_in_stream()
347 TAILQ_INSERT_TAIL(q, control, next_instrm); in sctp_place_control_in_stream()
348 control->on_strm_q = SCTP_ON_UNORDERED; in sctp_place_control_in_stream()
355 control->end_added = 1; in sctp_place_control_in_stream()
356 control->first_frag_seen = 1; in sctp_place_control_in_stream()
357 control->last_frag_seen = 1; in sctp_place_control_in_stream()
361 TAILQ_INSERT_HEAD(q, control, next_instrm); in sctp_place_control_in_stream()
363 control->on_strm_q = SCTP_ON_UNORDERED; in sctp_place_control_in_stream()
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H A Dsctputil.c281 sctp_log_strm_del(struct sctp_queued_to_read *control, struct sctp_queued_to_read *poschk, int from) in sctp_log_strm_del() argument
286 if (control == NULL) { in sctp_log_strm_del()
290 sctp_clog.x.strlog.stcb = control->stcb; in sctp_log_strm_del()
291 sctp_clog.x.strlog.n_tsn = control->sinfo_tsn; in sctp_log_strm_del()
292 sctp_clog.x.strlog.n_sseq = (uint16_t)control->mid; in sctp_log_strm_del()
293 sctp_clog.x.strlog.strm = control->sinfo_stream; in sctp_log_strm_del()
3142 struct sctp_queued_to_read *control; in sctp_notify_assoc_change() local
3227 control = sctp_build_readq_entry(stcb, stcb->asoc.primary_destination, in sctp_notify_assoc_change()
3230 if (control != NULL) { in sctp_notify_assoc_change()
3231 control->length = SCTP_BUF_LEN(m_notify); in sctp_notify_assoc_change()
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/src/contrib/sendmail/contrib/
H A Dsmcontrol.pl208 my $control = shift;
247 my $control = shift;
250 if (not defined $control)
254 return &do_command($control, "SHUTDOWN");
270 my $control = shift;
273 if (not defined $control)
277 return &do_command($control, "RESTART");
293 my $control = shift;
296 if (not defined $control)
300 return &do_command($control, "MEMDUMP");
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/src/tools/tools/ath/athprom/
H A Deeprom-320 | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 |
21 | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 |
22 | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 |
23 | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 |
24 | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 |
25 | Antenna control 10 $antennaControl10 | |
86 | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 |
87 | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 |
88 | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 |
89 | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 |
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H A Deeprom-423 | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 |
24 | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 |
25 | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 |
26 | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 |
27 | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 |
28 | Antenna control 10 $antennaControl10 | |
96 | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 |
97 | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 |
98 | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 |
99 | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 |
[all …]
H A Deeprom-527 | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 |
28 | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 |
29 | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 |
30 | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 |
31 | Antenna control 8 $antennaControl8 | Antenna control 9 $antennaControl9 |
32 | Antenna control 10 $antennaControl10 | |
113 | Antenna control 0 $antennaControl0 | Antenna control 1 $antennaControl1 |
114 | Antenna control 2 $antennaControl2 | Antenna control 3 $antennaControl3 |
115 | Antenna control 4 $antennaControl4 | Antenna control 5 $antennaControl5 |
116 | Antenna control 6 $antennaControl6 | Antenna control 7 $antennaControl7 |
[all …]
/src/sys/contrib/device-tree/Bindings/net/
H A Dmicrel-ksz90x1.txt14 All skew control options are specified in picoseconds. The minimum
48 - rxc-skew-ps : Skew control of RXC pad
49 - rxdv-skew-ps : Skew control of RX CTL pad
50 - txc-skew-ps : Skew control of TXC pad
51 - txen-skew-ps : Skew control of TX CTL pad
52 - rxd0-skew-ps : Skew control of RX data 0 pad
53 - rxd1-skew-ps : Skew control of RX data 1 pad
54 - rxd2-skew-ps : Skew control of RX data 2 pad
55 - rxd3-skew-ps : Skew control of RX data 3 pad
56 - txd0-skew-ps : Skew control of TX data 0 pad
[all …]
/src/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2hk-clocks.dtsi15 reg-names = "control";
23 reg-names = "control", "multiplier", "post-divider";
32 reg-names = "control";
41 reg-names = "control";
50 reg-names = "control";
59 reg-names = "control", "domain";
69 reg-names = "control", "domain";
79 reg-names = "control", "domain";
89 reg-names = "control", "domain";
99 reg-names = "control", "domain";
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H A Dkeystone-k2l-clocks.dtsi15 reg-names = "control";
23 reg-names = "control", "multiplier", "post-divider";
32 reg-names = "control";
41 reg-names = "control";
49 reg-names = "control", "domain";
60 reg-names = "control", "domain";
70 reg-names = "control", "domain";
80 reg-names = "control", "domain";
90 reg-names = "control", "domain";
100 reg-names = "control", "domain";
[all …]
H A Dkeystone-clocks.dtsi166 reg-names = "control", "domain";
177 reg-names = "control", "domain";
187 reg-names = "control", "domain";
198 reg-names = "control", "domain";
208 reg-names = "control", "domain";
218 reg-names = "control", "domain";
228 reg-names = "control", "domain";
238 reg-names = "control", "domain";
248 reg-names = "control", "domain";
258 reg-names = "control", "domain";
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/src/sys/cam/ctl/
H A Dctl_util.c99 ctl_scsi_tur(union ctl_io *io, ctl_tag_type tag_type, uint8_t control) in ctl_scsi_tur() argument
111 cdb->control = control; in ctl_scsi_tur()
125 uint8_t control) in ctl_scsi_inquiry() argument
139 cdb->control = control; in ctl_scsi_inquiry()
155 uint8_t control) in ctl_scsi_request_sense() argument
168 cdb->control = control; in ctl_scsi_request_sense()
184 uint8_t control) in ctl_scsi_report_luns() argument
198 cdb->control = control; in ctl_scsi_report_luns()
214 ctl_tag_type tag_type, uint8_t control) in ctl_scsi_read_write_buffer() argument
234 cdb->control = control; in ctl_scsi_read_write_buffer()
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H A Dctl_util.h45 void ctl_scsi_tur(union ctl_io *io, ctl_tag_type tag_type, uint8_t control);
48 uint8_t control);
51 ctl_tag_type tag_type, uint8_t control);
54 ctl_tag_type tag_type, uint8_t control);
59 uint8_t control);
64 uint8_t control);
68 ctl_tag_type tag_type, uint8_t control);
71 int pmi, ctl_tag_type tag_type, uint8_t control);
74 int pmi, ctl_tag_type tag_type, uint8_t control);
79 uint8_t control);
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/src/contrib/tcpdump/
H A Dprint-llc.c152 uint16_t control; in llc_print() local
177 control = GET_U_1(p + 2); in llc_print()
178 if ((control & LLC_U_FMT) == LLC_U_FMT) { in llc_print()
203 control = GET_LE_U_2(p + 2); in llc_print()
244 ND_PRINT(", ctrl 0x%02x: ", control); in llc_print()
246 ND_PRINT(", ctrl 0x%04x: ", control); in llc_print()
258 && control == LLC_UI) { in llc_print()
276 control == LLC_UI) { in llc_print()
282 control == LLC_UI) { in llc_print()
294 control == LLC_UI) { in llc_print()
[all …]
/src/contrib/unbound/doc/
H A Dunbound-control.rst37 .. program:: unbound-control
39 unbound-control(8)
45 **unbound-control** [``-hq``] [``-c cfgfile``] [``-s server``] command
50 ``unbound-control`` performs remote administration on the
82 @@UAHL@unbound-control.commands@start@@
91 @@UAHL@unbound-control.commands@stop@@
96 @@UAHL@unbound-control.commands@reload@@
101 @@UAHL@unbound-control.commands@reload_keep_cache@@
108 @@UAHL@unbound-control.commands@fast_reload@@ [``+dpv``]
138 :ref:`access-control<unbound.conf.access-control>` and similar options,
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/src/lib/msun/amd64/
H A Dfenv.c132 __uint16_t control; in __feenableexcept() local
135 __fnstcw(&control); in __feenableexcept()
137 omask = ~(control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT; in __feenableexcept()
138 control &= ~mask; in __feenableexcept()
139 __fldcw(&control); in __feenableexcept()
149 __uint16_t control; in __fedisableexcept() local
152 __fnstcw(&control); in __fedisableexcept()
154 omask = ~(control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT; in __fedisableexcept()
155 control |= mask; in __fedisableexcept()
156 __fldcw(&control); in __fedisableexcept()
/src/sys/dev/sound/pci/
H A Dhdsp.c235 hdsp_control_input_level(uint32_t control) in hdsp_control_input_level() argument
237 switch (control & HDSP_INPUT_LEVEL_MASK) { in hdsp_control_input_level()
256 uint32_t control; in hdsp_sysctl_input_level() local
265 control = sc->ctrl_register & HDSP_INPUT_LEVEL_MASK; in hdsp_sysctl_input_level()
266 label = hdsp_control_input_level(control); in hdsp_sysctl_input_level()
278 control = HDSP_INPUT_LEVEL_LOWGAIN; in hdsp_sysctl_input_level()
281 control = HDSP_INPUT_LEVEL_PLUS4DBU; in hdsp_sysctl_input_level()
284 control = HDSP_INPUT_LEVEL_MINUS10DBV; in hdsp_sysctl_input_level()
287 control &= HDSP_INPUT_LEVEL_MASK; in hdsp_sysctl_input_level()
288 if (control != (sc->ctrl_register & HDSP_INPUT_LEVEL_MASK)) { in hdsp_sysctl_input_level()
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/src/contrib/atf/atf-c/
H A Dutils_test.c406 const pid_t control = fork(); in ATF_TC_BODY() local
407 ATF_REQUIRE(control != -1); in ATF_TC_BODY()
408 if (control == 0) in ATF_TC_BODY()
412 ATF_REQUIRE(waitpid(control, &status, 0) != -1); in ATF_TC_BODY()
450 const pid_t control = fork(); in ATF_TC_BODY() local
451 ATF_REQUIRE(control != -1); in ATF_TC_BODY()
452 if (control == 0) in ATF_TC_BODY()
456 ATF_REQUIRE(waitpid(control, &status, 0) != -1); in ATF_TC_BODY()
465 const pid_t control = fork(); in ATF_TC_BODY() local
466 ATF_REQUIRE(control != -1); in ATF_TC_BODY()
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/src/contrib/atf/atf-c++/
H A Dutils_test.cpp346 const pid_t control = fork(); in ATF_TEST_CASE_BODY() local
347 ATF_REQUIRE(control != -1); in ATF_TEST_CASE_BODY()
348 if (control == 0) in ATF_TEST_CASE_BODY()
352 ATF_REQUIRE(waitpid(control, &status, 0) != -1); in ATF_TEST_CASE_BODY()
390 const pid_t control = fork(); in ATF_TEST_CASE_BODY() local
391 ATF_REQUIRE(control != -1); in ATF_TEST_CASE_BODY()
392 if (control == 0) in ATF_TEST_CASE_BODY()
396 ATF_REQUIRE(waitpid(control, &status, 0) != -1); in ATF_TEST_CASE_BODY()
405 const pid_t control = fork(); in ATF_TEST_CASE_BODY() local
406 ATF_REQUIRE(control != -1); in ATF_TEST_CASE_BODY()
[all …]
/src/lib/msun/i387/
H A Dfenv.c186 __uint16_t control; in __feenableexcept() local
189 __fnstcw(&control); in __feenableexcept()
194 omask = ~(control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT; in __feenableexcept()
195 control &= ~mask; in __feenableexcept()
196 __fldcw(&control); in __feenableexcept()
208 __uint16_t control; in __fedisableexcept() local
211 __fnstcw(&control); in __fedisableexcept()
216 omask = ~(control | mxcsr >> _SSE_EMASK_SHIFT) & FE_ALL_EXCEPT; in __fedisableexcept()
217 control |= mask; in __fedisableexcept()
218 __fldcw(&control); in __fedisableexcept()
/src/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DNativeRegisterContextDBReg_arm64.cpp88 m_hbp_regs[bp_index].control = control_value; in SetHardwareBreakpoint()
95 m_hbp_regs[bp_index].control &= ~1; in SetHardwareBreakpoint()
125 uint32_t tempControl = m_hbp_regs[hw_idx].control; in ClearHardwareBreakpoint()
127 m_hbp_regs[hw_idx].control &= ~g_enable_bit; in ClearHardwareBreakpoint()
134 m_hbp_regs[hw_idx].control = tempControl; in ClearHardwareBreakpoint()
181 uint32_t tempControl = m_hbp_regs[i].control; in ClearAllHardwareBreakpoints()
184 m_hbp_regs[i].control &= ~g_enable_bit; in ClearAllHardwareBreakpoints()
191 m_hbp_regs[i].control = tempControl; in ClearAllHardwareBreakpoints()
203 if ((m_hbp_regs[bp_index].control & g_enable_bit) != 0) in BreakpointIsEnabled()
296 m_hwp_regs[wp_index].control = control_value; in SetHardwareWatchpoint()
[all …]
/src/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-dfll.txt9 control module that will automatically adjust the VDD_CPU voltage by
17 - registers for the DFLL control logic.
25 - soc: Clock source for the DFLL control logic.
31 - dvco: Reset control for the DFLL DVCO.
36 the I2C register, control values and supported voltages.
38 Required properties for the control loop parameters:
39 - nvidia,sample-rate: Sample rate of the DFLL control loop.
46 Optional properties for the control loop parameters:
50 - nvidia,pwm-to-pmic: Use PWM to control regulator rather then I2C.
58 control is disabled and the PWM output is tristated. Note that this voltage is
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/src/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy.txt7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
24 omap_control_usb: omap-control-usb@4a002300 {
25 compatible = "ti,control-phy-otghs";
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/src/tools/tools/locale/etc/charmaps/
H A DISO8859-5.TXT40 # control characters.
177 0x80 0x0080 # <control>
178 0x81 0x0081 # <control>
179 0x82 0x0082 # <control>
180 0x83 0x0083 # <control>
181 0x84 0x0084 # <control>
182 0x85 0x0085 # <control>
183 0x86 0x0086 # <control>
184 0x87 0x0087 # <control>
185 0x88 0x0088 # <control>
[all …]
/src/sys/contrib/device-tree/Bindings/arm/
H A Dsyna.txt32 * Marvell Berlin CPU control bindings
34 CPU control register allows various operations on CPUs, like resetting them
48 * Marvell Berlin2 chip control binding
50 Marvell Berlin SoCs have a chip control register set providing several
53 chip control registers, so there should be a single DT node only providing the
61 BG2/BG2CD: chip control register set
62 BG2Q: chip control register set and cpu pll registers
64 * Marvell Berlin2 system control binding
66 Marvell Berlin SoCs have a system control register set providing several
73 - reg: address and length of the system control register set
[all …]

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