Searched refs:code_properties (Results 1 – 7 of 7) sorted by relevance
1380 Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64; in getAmdKernelCode()1384 AMD_HSA_BITS_SET(Out.code_properties, AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE, in getAmdKernelCode()1389 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER; in getAmdKernelCode()1393 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR; in getAmdKernelCode()1396 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR; in getAmdKernelCode()1399 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR; in getAmdKernelCode()1402 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID; in getAmdKernelCode()1405 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT; in getAmdKernelCode()1408 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE; in getAmdKernelCode()1411 Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR; in getAmdKernelCode()[all …]
562 uint32_t code_properties; member
33 printBitField<FLD_T(code_properties),\40 parseBitField<FLD_T(code_properties),\
48 uint32_t code_properties = 0; member
506 const MCExpr *CodeProps = MCConstantExpr::create(code_properties, Ctx); in EmitKernelCodeT()515 OS.emitIntValue(code_properties, /*Size=*/4); in EmitKernelCodeT()
1255 KernelCode.code_properties |= AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32; in initDefaultAMDKernelCodeT()
5934 if (C.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) { in ParseAMDKernelCodeTValue()