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/src/sys/contrib/dev/broadcom/brcm80211/brcmfmac/
H A Dchip.c223 struct brcmf_chip_priv *chip; member
256 ci = core->chip; in brcmf_chip_sb_iscoreup()
270 ci = core->chip; in brcmf_chip_ai_iscoreup()
286 ci = core->chip; in brcmf_chip_sb_coredisable()
356 ci = core->chip; in brcmf_chip_ai_coredisable()
391 ci = core->chip; in brcmf_chip_sb_resetcore()
442 ci = core->chip; in brcmf_chip_ai_resetcore()
516 core->chip = ci; in brcmf_chip_add_core()
570 return core->chip->ops->read32(core->chip->ctx, core->pub.base + reg); in brcmf_chip_core_read32()
576 core->chip->ops->write32(core->chip->ctx, core->pub.base + reg, val); in brcmf_chip_core_write32()
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H A Dchip.h29 u32 chip; member
69 int (*reset)(void *ctx, struct brcmf_chip *chip);
70 int (*setup)(void *ctx, struct brcmf_chip *chip);
71 void (*activate)(void *ctx, struct brcmf_chip *chip, u32 rstvec);
77 void brcmf_chip_detach(struct brcmf_chip *chip);
78 struct brcmf_core *brcmf_chip_get_core(struct brcmf_chip *chip, u16 coreid);
80 struct brcmf_core *brcmf_chip_get_chipcommon(struct brcmf_chip *chip);
/src/sys/contrib/dev/rtw88/
H A Dcoex.h330 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_init() local
332 chip->ops->coex_set_init(rtwdev); in rtw_coex_set_init()
338 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_ant_switch() local
340 if (!chip->ops->coex_set_ant_switch) in rtw_coex_set_ant_switch()
343 chip->ops->coex_set_ant_switch(rtwdev, ctrl_type, pos_type); in rtw_coex_set_ant_switch()
348 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_gnt_fix() local
350 chip->ops->coex_set_gnt_fix(rtwdev); in rtw_coex_set_gnt_fix()
355 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_gnt_debug() local
357 chip->ops->coex_set_gnt_debug(rtwdev); in rtw_coex_set_gnt_debug()
362 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_set_rfe_type() local
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H A Dcoex.c16 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_next_rssi_state() local
17 u8 tol = chip->rssi_tolerance; in rtw_coex_next_rssi_state()
39 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_limited_tx() local
44 if (!chip->scbd_support) in rtw_coex_limited_tx()
368 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_write_scbd() local
373 if (!chip->scbd_support) in rtw_coex_write_scbd()
381 if (!chip->new_scbd10_def && (bitpos & COEX_SCBD_FIX2M)) { in rtw_coex_write_scbd()
403 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_read_scbd() local
405 if (!chip->scbd_support) in rtw_coex_read_scbd()
413 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_coex_check_rfk() local
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H A Dmac.c169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling()
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D) in rtw_pwr_cmd_polling()
274 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_mac_power_switch() local
294 chip->id != RTW_CHIP_TYPE_8814A && in rtw_mac_power_switch()
311 pwr_seq = pwr_on ? chip->pwr_on_seq : chip->pwr_off_seq; in rtw_mac_power_switch()
315 if (chip->id == RTW_CHIP_TYPE_8822C || in rtw_mac_power_switch()
316 chip->id == RTW_CHIP_TYPE_8822B || in rtw_mac_power_switch()
317 chip->id == RTW_CHIP_TYPE_8821C) in rtw_mac_power_switch()
332 u8 sys_func_en = rtwdev->chip->sys_func_en; in __rtw_mac_init_system_cfg()
649 const struct rtw_chip_info *chip = rtwdev->chip; in download_firmware_to_mem() local
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H A Dphy.c162 const struct rtw_hw_reg_offset *edcca_th = rtwdev->chip->edcca_th; in rtw_phy_set_edcca_th()
177 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_set_mode() local
190 dm_info->l2h_th_ini = chip->l2h_th_ini_ad; in rtw_phy_adaptivity_set_mode()
194 dm_info->l2h_th_ini = chip->l2h_th_ini_cs; in rtw_phy_adaptivity_set_mode()
204 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_adaptivity_init() local
207 if (chip->ops->adaptivity_init) in rtw_phy_adaptivity_init()
208 chip->ops->adaptivity_init(rtwdev); in rtw_phy_adaptivity_init()
213 if (rtwdev->chip->ops->adaptivity) in rtw_phy_adaptivity()
214 rtwdev->chip->ops->adaptivity(rtwdev); in rtw_phy_adaptivity()
219 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_phy_cfo_init() local
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H A Drtw88xxa.c137 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A) in rtw88xxa_read_usb_type()
142 if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A) in rtw88xxa_read_usb_type()
202 const struct rtw_chip_info *chip = rtwdev->chip; in rtw88xxa_read_efuse() local
207 if (chip->id == RTW_CHIP_TYPE_8812A) in rtw88xxa_read_efuse()
212 log_map, chip->log_efuse_size, true); in rtw88xxa_read_efuse()
224 if (chip->id == RTW_CHIP_TYPE_8812A) { in rtw88xxa_read_efuse()
243 if (chip->id == RTW_CHIP_TYPE_8821A) in rtw88xxa_read_efuse()
262 if (chip->id == RTW_CHIP_TYPE_8821A) in rtw88xxa_read_efuse()
280 const struct rtw_chip_info *chip = rtwdev->chip; in rtw88xxa_reset_8051() local
285 if (chip->id == RTW_CHIP_TYPE_8812A) in rtw88xxa_reset_8051()
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H A Dmain.c494 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_fwcd_prep() local
496 const struct rtw_fwcd_segs *segs = chip->fwcd_segs; in rtw_fwcd_prep()
497 u32 prep_size = chip->fw_rxff_size + sizeof(struct rtw_fwcd_hdr); in rtw_fwcd_prep()
573 u32 size = rtwdev->chip->fw_rxff_size; in rtw_fw_dump_crash_log()
604 u32 rxff = rtwdev->chip->fw_rxff_size; in rtw_dump_fw()
954 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_set_channel() local
974 chip->ops->set_channel(rtwdev, center_chan, bandwidth, in rtw_set_channel()
998 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_chip_prepare_tx() local
1002 chip->ops->phy_calibration(rtwdev); in rtw_chip_prepare_tx()
1067 const struct rtw_chip_info *chip = rtwdev->chip; in rtw_hw_config_rf_ant_num() local
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/src/sys/dev/wbwd/
H A Dwbwd.c100 enum chips chip; member
126 enum chips chip; member
131 .chip = w83627hf,
136 .chip = w83627s,
141 .chip = w83697hf,
146 .chip = w83697ug,
151 .chip = w83637hf,
156 .chip = w83627thf,
161 .chip = w83687thf,
166 .chip = w83627ehf,
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/src/contrib/ofed/libcxgb4/
H A Dt4_chip_type.h75 static inline int is_t4(enum chip_type chip) in is_t4() argument
77 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); in is_t4()
80 static inline int is_t5(enum chip_type chip) in is_t5() argument
82 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5()
85 static inline int is_t6(enum chip_type chip) in is_t6() argument
87 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); in is_t6()
90 static inline int is_t7(enum chip_type chip) in is_t7() argument
92 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T7); in is_t7()
/src/sys/dev/ata/chipsets/
H A Data-acerlabs.c92 if (!(ctlr->chip = ata_match_chip(dev, ids))) in ata_ali_probe()
111 switch (ctlr->chip->cfg2) { in ata_ali_chipinit()
113 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
142 if (ctlr->chip->chiprev < 0xc7) in ata_ali_chipinit()
148 (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1); in ata_ali_chipinit()
151 if (ctlr->chip->chiprev <= 0xc4) in ata_ali_chipinit()
177 if (ctlr->chip->cfg2 == ALI_SATA) { in ata_ali_chipdeinit()
201 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) in ata_ali_ch_attach()
204 if (ctlr->chip->chiprev <= 0xc4) { in ata_ali_ch_attach()
209 if (ctlr->chip->cfg2 & ALI_NEW) in ata_ali_ch_attach()
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H A Data-siliconimage.c94 if (!(ctlr->chip = ata_match_chip(dev, ids))) in ata_sii_probe()
110 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
116 if (ctlr->chip->chipid != ATA_SII0680 || in ata_sii_chipinit()
121 if (ctlr->chip->cfg2 & SII_SETCLK) { in ata_sii_chipinit()
127 ctlr->chip->text); in ata_sii_chipinit()
131 if (ctlr->chip->cfg2 & SII_4CH) { in ata_sii_chipinit()
148 if (ctlr->chip->max_dma >= ATA_SA150) { in ata_sii_chipinit()
184 if (ctlr->chip->cfg2 & SII_INTR) in ata_cmd_ch_attach()
223 mode = min(mode, ctlr->chip->max_dma); in ata_cmd_setmode()
265 if (ctlr->chip->max_dma >= ATA_SA150) { in ata_sii_ch_attach()
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/src/sys/contrib/device-tree/Bindings/mtd/
H A Dfsl-upm-nand.txt5 - reg : should specify localbus chip select and size used for the chip.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
55 /* Multi-chip NAND device */
/src/sys/contrib/dev/rtw89/
H A Dphy.h566 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write8()
574 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write16()
582 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32()
590 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32_set()
598 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32_clr()
606 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_write32_mask()
613 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read8()
620 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read16()
627 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read32()
635 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy_read32_mask()
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H A Defuse.c51 if (rtwdev->chip->chip_id != RTL8852A) in rtw89_switch_efuse_bank()
80 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_enable_efuse_pwr_cut_ddv()
99 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; in rtw89_disable_efuse_pwr_cut_ddv()
226 u32 physical_size = rtwdev->chip->physical_efuse_size; in rtw89_dump_logical_efuse_map()
227 u32 logical_size = rtwdev->chip->logical_efuse_size; in rtw89_dump_logical_efuse_map()
228 u8 sec_ctrl_size = rtwdev->chip->sec_ctrl_efuse_size; in rtw89_dump_logical_efuse_map()
268 u32 phy_size = rtwdev->chip->physical_efuse_size; in rtw89_parse_efuse_map_ax()
269 u32 log_size = rtwdev->chip->logical_efuse_size; in rtw89_parse_efuse_map_ax()
270 u32 dav_phy_size = rtwdev->chip->dav_phy_efuse_size; in rtw89_parse_efuse_map_ax()
271 u32 dav_log_size = rtwdev->chip->dav_log_efuse_size; in rtw89_parse_efuse_map_ax()
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H A Defuse_be.c25 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_enable_efuse_pwr_cut_ddv_be() local
29 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) in rtw89_enable_efuse_pwr_cut_ddv_be()
46 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_disable_efuse_pwr_cut_ddv_be() local
50 if (chip->chip_id == RTL8922A && hal->cv == CHIP_CAV) in rtw89_disable_efuse_pwr_cut_ddv_be()
219 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_eeprom_parser_be() local
238 phy_idx = chip->sec_ctrl_efuse_size; in rtw89_eeprom_parser_be()
310 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_parse_logical_efuse_block_be() local
315 efuse_block = &chip->efuse_blocks[block]; in rtw89_parse_logical_efuse_block_be()
329 ret = rtwdev->chip->ops->read_efuse(rtwdev, log_map, block); in rtw89_parse_logical_efuse_block_be()
343 u32 phy_size = rtwdev->chip->physical_efuse_size; in rtw89_parse_efuse_map_be()
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H A Dmac.c45 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; in rtw89_mac_mem_write()
55 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; in rtw89_mac_mem_read()
307 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; in rtw89_mac_dump_l0_to_l1()
325 const struct rtw89_chip_info *chip = rtwdev->chip; in rtw89_mac_dump_dmac_err_status() local
345 if (chip->chip_id == RTL8852C) { in rtw89_mac_dump_dmac_err_status()
362 if (chip->chip_id == RTL8852C) in rtw89_mac_dump_dmac_err_status()
371 if (chip->chip_id == RTL8852C) { in rtw89_mac_dump_dmac_err_status()
403 } else if (chip->chip_id == RTL8922A) { in rtw89_mac_dump_dmac_err_status()
454 if (chip->chip_id == RTL8922A) { in rtw89_mac_dump_dmac_err_status()
479 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { in rtw89_mac_dump_dmac_err_status()
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/src/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
30 "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
31 "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
34 "mediatek,<chip>-disp-ccorr" - color correction
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
37 "mediatek,<chip>-disp-aal" - adaptive ambient light controller
38 "mediatek,<chip>-disp-gamma" - gamma correction
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/src/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dpixcir_i2c_ts.txt5 - reg: I2C address of the chip
6 - interrupts: interrupt to which the chip is connected
7 - attb-gpio: GPIO connected to the ATTB line of the chip
12 - reset-gpios: GPIO connected to the RESET line of the chip
13 - enable-gpios: GPIO connected to the ENABLE line of the chip
14 - wake-gpios: GPIO connected to the WAKE line of the chip
/src/sys/contrib/device-tree/Bindings/net/nfc/
H A Dnfcmrvl.txt12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
17 - break-control: Specifies that the chip needs specific break management.
19 Optional I2C-based chip specific properties:
20 - i2c-int-falling: Specifies that the chip read event shall be trigged on
22 - i2c-int-rising: Specifies that the chip read event shall be trigged on
/src/sys/contrib/device-tree/Bindings/power/reset/
H A Docelot-reset.txt11 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
12 "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
16 compatible = "mscc,ocelot-chip-reset";
H A Dltc2952-poweroff.txt3 This chip is used to externally trigger a system shut down. Once the trigger has
4 been sent, the chip's watchdog has to be reset to gracefully shut down.
11 chip's watchdog line
13 chip's kill line
17 chip's trigger line. If this property is not set, the
18 trigger function is ignored and the chip is kept alive
/src/sys/contrib/device-tree/Bindings/mips/cavium/
H A Dbootbus.txt3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
23 The configuration parameters for each chip select are stored in child
29 - cavium,cs-index: A single cell indicating the chip select that
60 the bus for this chip select.
72 /* The chip select number and offset */
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/src/sys/contrib/device-tree/Bindings/spi/
H A Dspi-sprd-adi.txt4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
19 the analog chip address where user want to access by hardware components.
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
36 - #address-cells: Number of cells required to define a chip select address
38 - #size-cells: Size of cells required to define a chip select address size
48 value specifies the analog chip address where user want to access
/src/sys/contrib/device-tree/src/arm/aspeed/
H A Dibm-power10-quad.dtsi17 chip-id = <0>;
45 chip-id = <0>;
73 chip-id = <0>;
101 chip-id = <0>;
129 chip-id = <0>;
157 chip-id = <0>;
185 chip-id = <0>;
213 chip-id = <0>;
241 chip-id = <0>;
269 chip-id = <0>;
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