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Searched refs:bus_width (Results 1 – 25 of 32) sorted by relevance

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/src/sys/dev/bhnd/nvram/
H A Dbhnd_nvram_iores.c52 u_int bus_width; /**< data type byte width to be used member
77 bus_size_t size, u_int bus_width) in bhnd_nvram_iores_new() argument
83 switch (bus_width) { in bhnd_nvram_iores_new()
90 BHND_NV_LOG("invalid bus width %u\n", bus_width); in bhnd_nvram_iores_new()
117 if ((r_start + offset) % bus_width != 0) { in bhnd_nvram_iores_new()
119 "%u\n", (uintmax_t)r_start, (uintmax_t)offset, bus_width); in bhnd_nvram_iores_new()
123 if (size % bus_width != 0) { in bhnd_nvram_iores_new()
125 (uintmax_t)size, bus_width); in bhnd_nvram_iores_new()
135 iores->bus_width = bus_width; in bhnd_nvram_iores_new()
199 if (offset % iores->bus_width != 0) in bhnd_nvram_iores_validate_req()
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H A Dbhnd_nvram_io.h60 u_int bus_width);
/src/sys/dev/mmc/
H A Dmmc_helpers.c89 uint32_t bus_width, max_freq; in mmc_parse() local
91 bus_width = 0; in mmc_parse()
92 if (device_get_property(dev, "bus-width", &bus_width, in mmc_parse()
93 sizeof(bus_width), DEVICE_PROP_UINT32) <= 0) in mmc_parse()
94 bus_width = 1; in mmc_parse()
96 if (bus_width >= 4) in mmc_parse()
98 if (bus_width >= 8) in mmc_parse()
H A Dmmc.c94 enum mmc_bus_width bus_width; /* Bus width to use */ member
369 (ivar->bus_width == bus_width_4) ? 4 : in mmc_acquire_bus()
370 (ivar->bus_width == bus_width_8) ? 8 : 1, in mmc_acquire_bus()
380 mmcbr_set_bus_width(busdev, ivar->bus_width); in mmc_acquire_bus()
764 switch (ivar->bus_width) { in mmc_set_card_bus_width()
777 switch (ivar->bus_width) { in mmc_set_card_bus_width()
830 enum mmc_bus_width bus_width; in mmc_set_power_class() local
834 bus_width = ivar->bus_width; in mmc_set_power_class()
836 timing == bus_timing_normal || bus_width == bus_width_1) in mmc_set_power_class()
848 bus_width >= bus_width_4) in mmc_set_power_class()
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H A Dmmcvar.h92 MMC_ACCESSOR(bus_width, BUS_WIDTH, int)
H A Dmmcbrvar.h90 MMCBR_ACCESSOR(bus_width, BUS_WIDTH, int) in MMCBR_ACCESSOR()
H A Dbridge.h133 enum mmc_bus_width bus_width; member
H A Dmmcreg.h698 uint8_t bus_width; member
H A Dmmcspi.c538 *result = slot->host.ios.bus_width; in mmcspi_read_ivar()
605 slot->host.ios.bus_width = value; in mmcspi_write_ivar()
/src/sys/dev/aic7xxx/
H A Daic7xxx.c172 u_int bus_width);
176 u_int bus_width, u_int ppr_options);
1822 u_int *bus_width, role_t role) in ahc_validate_width() argument
1824 switch (*bus_width) { in ahc_validate_width()
1828 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; in ahc_validate_width()
1833 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; in ahc_validate_width()
1838 *bus_width = MIN(tinfo->user.width, *bus_width); in ahc_validate_width()
1840 *bus_width = MIN(tinfo->goal.width, *bus_width); in ahc_validate_width()
2479 u_int bus_width) in ahc_construct_wdtr() argument
2484 ahc->msgout_buf[ahc->msgout_index++] = bus_width; in ahc_construct_wdtr()
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H A Daic79xx.c145 u_int bus_width);
149 u_int bus_width, u_int ppr_options);
2977 u_int *bus_width, role_t role) in ahd_validate_width() argument
2979 switch (*bus_width) { in ahd_validate_width()
2983 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; in ahd_validate_width()
2988 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; in ahd_validate_width()
2993 *bus_width = MIN(tinfo->user.width, *bus_width); in ahd_validate_width()
2995 *bus_width = MIN(tinfo->goal.width, *bus_width); in ahd_validate_width()
3788 u_int bus_width) in ahd_construct_wdtr() argument
3793 ahd->msgout_buf[ahd->msgout_index++] = bus_width; in ahd_construct_wdtr()
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H A Daic79xx_osm.c789 &spi->bus_width, ROLE_UNKNOWN); in ahd_set_tran_settings()
790 ahd_set_width(ahd, &devinfo, spi->bus_width, in ahd_set_tran_settings()
821 if (spi->bus_width != MSG_EXT_WDTR_BUS_16_BIT) in ahd_set_tran_settings()
831 spi->bus_width, ROLE_UNKNOWN); in ahd_set_tran_settings()
892 spi->bus_width = tinfo->width; in ahd_get_tran_settings()
H A Daic7xxx_osm.c670 &spi->bus_width, ROLE_UNKNOWN); in ahc_action()
671 ahc_set_width(ahc, &devinfo, spi->bus_width, in ahc_action()
708 if (spi->bus_width != MSG_EXT_WDTR_BUS_16_BIT) in ahc_action()
716 spi->bus_width, ROLE_UNKNOWN); in ahc_action()
873 spi->bus_width = tinfo->width; in ahc_get_tran_settings()
H A Daic7xxx.h1292 u_int *bus_width,
/src/sys/dev/mmc/host/
H A Ddwmmc.c872 ios->clock, ios->bus_width, ios->timing); in dwmmc_update_ios()
887 if (ios->bus_width == bus_width_8) in dwmmc_update_ios()
889 else if (ios->bus_width == bus_width_4) in dwmmc_update_ios()
1314 *(int *)result = sc->host.ios.bus_width; in dwmmc_read_ivar()
1373 sc->host.ios.bus_width = value; in dwmmc_write_ivar()
1466 ios->bus_width = new_ios->bus_width; in dwmmc_set_tran_settings()
1468 device_printf(sc->dev, "Bus width => %d\n", ios->bus_width); in dwmmc_set_tran_settings()
/src/sys/dev/sdhci/
H A Dsdhci.c1379 if (ios->bus_width == bus_width_8) {
1382 } else if (ios->bus_width == bus_width_4) {
1385 } else if (ios->bus_width == bus_width_1) {
1389 panic("Invalid bus width: %d", ios->bus_width);
1514 ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 :
2462 *result = slot->host.ios.bus_width;
2553 slot->host.ios.bus_width = value;
2806 ios->bus_width = new_ios->bus_width;
2808 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2842 __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing);
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/src/sys/dev/jedec_dimm/
H A Djedec_dimm.c495 uint32_t bus_width; in jedec_dimm_capacity() local
563 bus_width = 1 << bus_width_byte; in jedec_dimm_capacity()
564 bus_width *= 8; in jedec_dimm_capacity()
637 *capacity_mb = sdram_capacity / 8 * bus_width / sdram_width * in jedec_dimm_capacity()
/src/sys/arm/allwinner/
H A Daw_mmc.c280 ios->bus_width = new_ios->bus_width; in aw_mmc_set_tran_settings()
282 device_printf(sc->aw_dev, "Bus width => %d\n", ios->bus_width); in aw_mmc_set_tran_settings()
1144 *(int *)result = sc->aw_host.ios.bus_width;
1208 sc->aw_host.ios.bus_width = value;
1340 switch (ios->bus_width) {
1415 ios->bus_width == bus_width_8)) {
/src/lib/libcam/
H A Dcamlib.c648 device->bus_width = spi->bus_width; in cam_real_open_device()
652 device->bus_width = 0; in cam_real_open_device()
H A Dcamlib.h121 uint8_t bus_width; /* Negotiated bus width */ member
/src/sys/cam/scsi/
H A Dscsi_xpt.c2882 spi->bus_width = cur_spi->bus_width; in scsi_set_transfer_settings()
2884 spi->bus_width = 0; in scsi_set_transfer_settings()
2900 switch (spi->bus_width) { in scsi_set_transfer_settings()
2913 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; in scsi_set_transfer_settings()
2920 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT; in scsi_set_transfer_settings()
2939 if (spi->bus_width == 0) in scsi_set_transfer_settings()
3149 *speed *= (0x01 << spi->bus_width); in _scsi_announce_periph()
3199 && spi->bus_width > 0) { in scsi_announce_periph_sbuf()
3205 sbuf_printf(sb, "%dbit)", 8 * (0x01 << spi->bus_width)); in scsi_announce_periph_sbuf()
/src/sys/dev/rtsx/
H A Drtsx.c1754 uint32_t bus_width; local
1758 bus_width = RTSX_BUS_WIDTH_1;
1761 bus_width = RTSX_BUS_WIDTH_4;
1764 bus_width = RTSX_BUS_WIDTH_8;
1769 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width);
1777 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]);
3003 ios->bus_width = new_ios->bus_width;
3006 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width);
3075 *result = sc->rtsx_host.ios.bus_width;
3144 sc->rtsx_host.ios.bus_width = value;
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/src/sbin/camcontrol/
H A Dcamcontrol.c1362 speed *= (0x01 << spi->bus_width); in camxferrate()
1411 && (spi->bus_width > 0)) { in camxferrate()
1418 fprintf(stdout, "%dbit)", 8 * (0x01 << spi->bus_width)); in camxferrate()
5331 (0x01 << spi->bus_width) * 8); in cts_print()
6148 int bus_width = -1; in ratecontrol() local
6224 bus_width = strtol(optarg, NULL, 0); in ratecontrol()
6225 if (bus_width < 0) { in ratecontrol()
6226 warnx("bus width %d is < 0", bus_width); in ratecontrol()
6396 if (spi && bus_width != -1) { in ratecontrol()
6403 if ((bus_width == 16) in ratecontrol()
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/src/sys/arm/ti/
H A Dti_sdhci.c369 if (ios->bus_width == bus_width_8) in ti_sdhci_update_ios()
/src/sys/dev/sym/
H A Dsym_defs.h197 u_char bus_width; /* 0x08/0x10 */ member

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