Home
last modified time | relevance | path

Searched refs:buildNot (Results 1 – 6 of 6) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp933 return MIB.buildNot(DstTy, FCmp).getReg(0); in getVectorFCMP()
1046 CmpRes = MIB.buildNot(DstTy, CmpRes).getReg(0); in applyLowerVectorFCMP()
H A DAArch64LegalizerInfo.cpp1429 MIRBuilder.buildNot(DstReg, CmpReg); in legalizeICMP()
/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp3539 auto Not = Builder.buildNot(MRI.getType(X), X); in applyXorOfAndWithSameReg()
6732 B.buildNot(Inner, Cond); in tryFoldSelectOfConstants()
6743 B.buildNot(Inner, Cond); in tryFoldSelectOfConstants()
6800 B.buildNot(Not, Cond); in tryFoldSelectOfConstants()
6864 B.buildNot(Inner, Cond); in tryFoldBoolSelectToLogic()
6880 B.buildNot(Inner, Cond); in tryFoldBoolSelectToLogic()
H A DLegalizerHelper.cpp3346 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); in buildBitFieldInsert()
6614 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); in lowerFunnelShiftWithInverse()
6652 auto NotZ = MIRBuilder.buildNot(ShTy, Z); in lowerFunnelShiftAsShifts()
8041 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; in lowerAddSubSatToMinMax()
8513 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h1820 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { in buildNot() function
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2542 auto Not = B.buildNot(S64, Shr); in legalizeIntrinsicTrunc()