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Searched refs:addUse (Results 1 – 25 of 56) sorted by relevance

123

/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp581 MIB.addDef(Call->ReturnRegister).addUse(TypeReg);
587 MIB.addUse(ArgReg);
605 .addUse(Call->Arguments[0]) in buildAtomicInitInst()
606 .addUse(Call->Arguments[1]); in buildAtomicInitInst()
644 .addUse(TypeReg) in buildAtomicLoadInst()
645 .addUse(PtrRegister) in buildAtomicLoadInst()
646 .addUse(ScopeRegister) in buildAtomicLoadInst()
647 .addUse(MemSemanticsReg); in buildAtomicLoadInst()
668 .addUse(PtrRegister) in buildAtomicStoreInst()
669 .addUse(ScopeRegister) in buildAtomicStoreInst()
[all …]
H A DSPIRVInstructionSelector.cpp374 .addUse(GR.getSPIRVTypeID(ResType)) in spvSelect()
375 .addUse(I.getOperand(1).getReg()) in spvSelect()
376 .addUse(I.getOperand(2).getReg()); in spvSelect()
558 .addUse(GR.getSPIRVTypeID(ResType)) in spvSelect()
561 .addUse(GV) in spvSelect()
562 .addUse(Idx) in spvSelect()
563 .addUse(I.getOperand(2).getReg()); in spvSelect()
647 .addUse(GR.getSPIRVTypeID(ResType)) in selectExtInst()
666 .addUse(GR.getSPIRVTypeID(ResType)) in selectUnOpWithSrc()
667 .addUse(SrcReg) in selectUnOpWithSrc()
[all …]
H A DSPIRVGlobalRegistry.cpp155 .addUse(getSPIRVTypeID(ElemType)) in getOpTypeVector()
249 .addUse(getSPIRVTypeID(SpvType)); in getOrCreateConstFP()
253 .addUse(getSPIRVTypeID(SpvType)); in getOrCreateConstFP()
283 .addUse(getSPIRVTypeID(SpvType)); in getOrCreateConstInt()
288 .addUse(getSPIRVTypeID(SpvType)); in getOrCreateConstInt()
327 .addUse(getSPIRVTypeID(SpvType)); in buildConstantInt()
332 .addUse(getSPIRVTypeID(SpvType)); in buildConstantInt()
364 .addUse(getSPIRVTypeID(SpvType)); in buildConstantFP()
422 .addUse(getSPIRVTypeID(SpvType)); in getOrCreateCompositeOrNull()
424 MIB.addUse(SpvScalConst); in getOrCreateCompositeOrNull()
[all …]
H A DSPIRVPreLegalizer.cpp396 .addUse(NewReg) in insertAssignInstr()
397 .addUse(GR->getSPIRVTypeID(SpirvTy)) in insertAssignInstr()
419 MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg()); in processInstr()
650 .addUse(GR->getSPIRVTypeID(RetType)) in insertInlineAsmProcess()
651 .addUse(GR->getSPIRVTypeID(FuncType)) in insertInlineAsmProcess()
652 .addUse(AsmTargetReg); in insertInlineAsmProcess()
666 .addUse(AsmReg) in insertInlineAsmProcess()
697 .addUse(GR->getSPIRVTypeID(RetType)) in insertInlineAsmProcess()
698 .addUse(AsmReg); in insertInlineAsmProcess()
704 AsmCall.addUse(MO.getReg()); in insertInlineAsmProcess()
[all …]
H A DSPIRVCallLowering.cpp52 .addUse(VRegs[0]) in lowerReturn()
397 .addUse(GR->getSPIRVTypeID(RetTy)) in lowerFormalArguments()
399 .addUse(GR->getSPIRVTypeID(FuncTy)); in lowerFormalArguments()
409 .addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i])); in lowerFormalArguments()
424 .addUse(FuncVReg); in lowerFormalArguments()
605 .addUse(GR->getSPIRVTypeID(RetType)) in lowerCall()
612 MIB.addUse(Arg.Regs[0]); in lowerCall()
H A DSPIRVUtils.cpp103 auto MIB = MIRBuilder.buildInstr(SPIRV::OpName).addUse(Target); in buildOpName()
121 .addUse(Reg) in buildOpDecorate()
131 .addUse(Reg) in buildOpDecorate()
150 .addUse(Reg) in buildOpSpirvDecorations()
H A DSPIRVISelLowering.cpp122 .addUse(GR.getSPIRVTypeID(NewPtrType)) in doInsertBitcast()
123 .addUse(OpReg) in doInsertBitcast()
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp280 .addUse(TiedDest) in buildUnalignedLoad()
335 .addUse(PseudoMULTuReg); in select()
370 .addUse(I.getOperand(2).getReg()) in select()
378 .addUse(I.getOperand(0).getReg()) in select()
379 .addUse(JTIndex); in select()
387 .addUse(DestAddress) in select()
399 .addUse(DestTmp) in select()
400 .addUse(MF.getInfo<MipsFunctionInfo>() in select()
408 .addUse(Dest); in select()
523 .addUse(HILOReg); in select()
[all …]
H A DMipsISelLowering.cpp4802 .addUse(Address) in emitLDR_W()
4804 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(Temp); in emitLDR_W()
4814 .addUse(Address) in emitLDR_W()
4816 .addUse(Undef); in emitLDR_W()
4819 .addUse(Address) in emitLDR_W()
4821 .addUse(LoadHalf); in emitLDR_W()
4822 BuildMI(*BB, I, DL, TII->get(Mips::FILL_W)).addDef(Dest).addUse(LoadFull); in emitLDR_W()
4849 .addUse(Address) in emitLDR_D()
4851 BuildMI(*BB, I, DL, TII->get(Mips::FILL_D)).addDef(Dest).addUse(Temp); in emitLDR_D()
4858 .addUse(Address) in emitLDR_D()
[all …]
H A DMipsSEISelDAGToDAG.cpp135 .addUse(Mips::RA_64, RegState::Undef) in emitMCountABI()
136 .addUse(Mips::ZERO_64); in emitMCountABI()
138 MIB.addUse(Mips::AT_64, RegState::Implicit); in emitMCountABI()
143 .addUse(Mips::RA, RegState::Undef) in emitMCountABI()
144 .addUse(Mips::ZERO); in emitMCountABI()
148 .addUse(Mips::SP) in emitMCountABI()
151 MIB.addUse(Mips::AT, RegState::Implicit); in emitMCountABI()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp233 .addUse(MisspeculatingTaintReg) in insertTrackingCode()
234 .addUse(AArch64::XZR) in insertTrackingCode()
373 .addUse(AArch64::SP) in insertSPToRegTaintPropagation()
379 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
380 .addUse(AArch64::XZR) in insertSPToRegTaintPropagation()
396 .addUse(AArch64::SP) in insertRegToSPTaintPropagation()
402 .addUse(TmpReg, RegState::Kill | RegState::Renamable) in insertRegToSPTaintPropagation()
403 .addUse(MisspeculatingTaintReg, RegState::Kill) in insertRegToSPTaintPropagation()
408 .addUse(TmpReg, RegState::Kill) in insertRegToSPTaintPropagation()
456 .addUse(Reg); in makeGPRSpeculationSafe()
[all …]
H A DAArch64ExpandPseudoInsts.cpp381 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
382 .addUse(AArch64::WZR) in expandCMP_SWAP_128()
389 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
390 .addUse(StatusReg, RegState::Kill) in expandCMP_SWAP_128()
393 .addUse(StatusReg, getKillRegState(StatusDead)) in expandCMP_SWAP_128()
927 .addUse(CtxReg) in expandStoreSwiftAsyncContext()
928 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
944 .addUse(BaseReg) in expandStoreSwiftAsyncContext()
949 .addUse(AArch64::X16) in expandStoreSwiftAsyncContext()
956 .addUse(AArch64::XZR) in expandStoreSwiftAsyncContext()
[all …]
H A DAArch64LowerHomogeneousPrologEpilog.cpp354 .addUse(AArch64::SP) in getOrCreateFrameHelper()
370 .addUse(AArch64::LR) in getOrCreateFrameHelper()
616 .addUse(AArch64::SP) in lowerProlog()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2503 .addUse(Hi) in extractF64Exponent()
2504 .addUse(Const0.getReg(0)) in extractF64Exponent()
2505 .addUse(Const1.getReg(0)); in extractF64Exponent()
2594 .addUse(Unmerge.getReg(1)); in legalizeITOFP()
2827 .addUse(MulVal.getReg(0)) in legalizeSinCos()
2836 .addUse(TrigVal) in legalizeSinCos()
3212 .addUse(PtrReg) in legalizeAtomicCmpXChg()
3213 .addUse(PackedVal) in legalizeAtomicCmpXChg()
3303 .addUse(Ext.getReg(0)) in legalizeFlog2()
3315 .addUse(Src) in legalizeFlog2()
[all …]
H A DAMDGPUPostLegalizerCombiner.cpp279 .addUse(SqrtSrcMI->getOperand(0).getReg()) in matchRcpSqrtToRsq()
289 .addUse(RcpSrcMI->getOperand(0).getReg()) in matchRcpSqrtToRsq()
310 .addUse(X) in applyFDivSqrtToRsqF16()
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ArgumentStackSlotRebase.cpp168 .addUse(X86::NoRegister) in runOnMachineFunction()
170 .addUse(X86::NoRegister) in runOnMachineFunction()
H A DX86FrameLowering.cpp1574 .addUse(StackPtr) in emitPrologue()
1576 .addUse(X86::NoRegister) in emitPrologue()
1578 .addUse(X86::NoRegister) in emitPrologue()
1615 .addUse(MachineFramePtr) in emitPrologue()
1616 .addUse(X86::RIP) in emitPrologue()
1618 .addUse(X86::NoRegister) in emitPrologue()
1621 .addUse(X86::NoRegister); in emitPrologue()
1631 .addUse(MachineFramePtr) in emitPrologue()
1802 .addUse(X86::RSP) in emitPrologue()
1804 .addUse(X86::NoRegister) in emitPrologue()
[all …]
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp583 .addUse(LHSReg) in insertComparison()
584 .addUse(RHSReg) in insertComparison()
602 .addUse(PrevRes) in insertComparison()
780 .addUse(CondReg) in selectSelect()
796 .addUse(TrueReg) in selectSelect()
797 .addUse(FalseReg) in selectSelect()
899 .addUse(AndResult) in select()
949 .addUse(SrcReg) in select()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp716 RegSequence.addUse(Regs[I]); in createTuple()
1065 .addUse(SrcReg) in selectCopy()
1930 Shl.addUse(Src2Reg); in selectVectorSHL()
2025 .addUse(ArgsAddrReg) in selectVaStartDarwin()
2026 .addUse(ListReg) in selectVaStartDarwin()
2053 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
2742 .addUse(SrcReg, 0, in select()
2808 .addUse(I.getOperand(2).getReg()) in select()
2970 .addUse(NewDst) in select()
2999 IsStore ? NewInst.addUse(CurValReg) : NewInst.addDef(CurValReg); in select()
[all …]
H A DAArch64LegalizerInfo.cpp1783 NewI.addUse(MI.getOperand(1).getReg()); in legalizeLoadStore()
1788 NewI.addUse(Base); in legalizeLoadStore()
2001 UADD = MIRBuilder.buildIntrinsic(Opc, {HTy}).addUse(HSum); in legalizeCTPOP()
2058 .addUse(DesiredI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
2060 .addUse(DesiredI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
2063 .addUse(NewI->getOperand(0).getReg()) in legalizeAtomicCmpxchg128()
2065 .addUse(NewI->getOperand(1).getReg()) in legalizeAtomicCmpxchg128()
/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp795 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
796 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
800 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
801 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
/src/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86CallLowering.cpp111 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
380 MIB.addUse(X86::AL, RegState::Implicit); in lowerCall()
/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp164 .addUse(Src); in repairReg()
198 MergeBuilder.addUse(SrcReg); in repairReg()
207 UnMergeBuilder.addUse(MO.getReg()); in repairReg()
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp53 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DValue.h505 void addUse(Use &U) { U.addToList(&UseList); } in addUse() function
885 if (V) V->addUse(*this); in set()

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