| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoZa.td | 25 let RenderMethod = "addRegOperands";
32 let RenderMethod = "addRegOperands";
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| H A D | RISCVInstrInfoD.td | 40 let RenderMethod = "addRegOperands";
47 let RenderMethod = "addRegOperands";
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| H A D | RISCVInstrInfoF.td | 84 let RenderMethod = "addRegOperands";
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| H A D | RISCVInstrInfoC.td | 751 let RenderMethod = "addRegOperands";
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| H A D | RISCVInstrInfo.td | 122 let RenderMethod = "addRegOperands";
1081 let RenderMethod = "addRegOperands";
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1019 void addRegOperands(MCInst &Inst, unsigned N) const;
1023 addRegOperands(Inst, N); in addRegOrImmOperands()
1032 addRegOperands(Inst, N); in addRegOrImmWithInputModsOperands()
1052 addRegOperands(Inst, N); in addRegWithInputModsOperands()
2477 void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in AMDGPUOperand
7030 Op.addRegOperands(Inst, 1); in cvtExp()
8304 Op.addRegOperands(Inst, 1); in cvtMubufImpl()
8309 Op.addRegOperands(Inst, 1); in cvtMubufImpl()
8546 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVOP3Interp()
8584 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1); in cvtVINTERP()
[all …]
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 194 let RenderMethod = "addRegOperands";
709 let RenderMethod = "addRegOperands";
758 let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {
809 let RenderMethod = "addRegOperands";
945 let RenderMethod = "addRegOperands";
986 let RenderMethod = "addRegOperands";
1150 let RenderMethod = "addRegOperands";
1530 let RenderMethod = "addRegOperands";
1588 let RenderMethod = "addRegOperands";
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| /src/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 161 void addRegOperands(MCInst &Inst, unsigned N) const;
320 void M68kOperand::addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in M68kOperand
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| /src/contrib/llvm-project/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 191 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
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| /src/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 127 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anondbd9a0c30111::MSP430Operand
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| /src/contrib/llvm-project/llvm/lib/Target/Xtensa/AsmParser/ |
| H A D | XtensaAsmParser.cpp | 334 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
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| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 300 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonced995d30111::SystemZOperand
1301 ZOperand.addRegOperands(Inst, 1); in ParseDirectiveInsn()
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| /src/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 135 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonc362e6e70111::AVROperand
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| /src/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 569 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
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| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.td | 41 let RenderMethod = "addRegOperands";
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 383 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
416 addRegOperands(Inst, N); in addsgp10ConstOperands()
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| /src/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmParser.cpp | 116 void addRegOperands(MCInst &, unsigned) const { in addRegOperands() function
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| /src/contrib/llvm-project/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 400 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
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| /src/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 96 let RenderMethod = "addRegOperands";
108 let RenderMethod = "addRegOperands";
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| /src/contrib/llvm-project/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 562 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
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| /src/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 387 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonbfe0d1470211::SparcOperand
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| /src/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 465 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon26aeac6b0211::VEOperand
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2599 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon288864d50111::ARMOperand
5817 ((ARMOperand &)*Operands[RegRd]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5827 ((ARMOperand &)*Operands[RegRn]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5829 ((ARMOperand &)*Operands[RegRm]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5907 ((ARMOperand &)*Operands[MnemonicOpsEndInd]).addRegOperands(Inst, 1); // Rt in cvtMVEVMOVQtoDReg()
5909 .addRegOperands(Inst, 1); // Rt2 in cvtMVEVMOVQtoDReg()
5911 .addRegOperands(Inst, 1); // Qd in cvtMVEVMOVQtoDReg()
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| /src/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 588 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonea21578f0111::LoongArchOperand
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| /src/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.td | 175 let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass]in {
|