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Searched refs:adap (Results 1 – 25 of 33) sorted by relevance

12

/src/sys/dev/cxgb/common/
H A Dcxgb_mc5.c133 adapter_t *adap = mc5->adapter; in init_mask_data_array() local
140 unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX); in init_mask_data_array()
148 dbgi_wr_data3(adap, 0, 0, 0); in init_mask_data_array()
150 if (mc5_write(adap, data_array_base + (i << addr_shift), in init_mask_data_array()
156 dbgi_wr_data3(adap, 0x3fffffff, 0xfff80000, 0xff); in init_mask_data_array()
157 if (mc5_write(adap, mask_array_base + (i << addr_shift), in init_mask_data_array()
161 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); in init_mask_data_array()
162 if (mc5_write(adap, mask_array_base + (i << addr_shift), in init_mask_data_array()
167 dbgi_wr_data3(adap, in init_mask_data_array()
171 if (mc5_write(adap, mask_array_base + (i << addr_shift), in init_mask_data_array()
[all …]
H A Dcxgb_xgmac.c48 adapter_t *adap = mac->adapter; in xgm_reset_ctrl() local
51 if (is_10G(adap)) { in xgm_reset_ctrl()
52 int cfg = t3_read_reg(adap, A_XGM_PORT_CFG + mac->offset); in xgm_reset_ctrl()
57 } else if (uses_xaui(adap)) in xgm_reset_ctrl()
73 adapter_t *adap = mac->adapter; in xaui_serdes_reset() local
76 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] | in xaui_serdes_reset()
80 (void)t3_read_reg(adap, ctrl); in xaui_serdes_reset()
84 t3_set_reg_field(adap, ctrl, clear[i], 0); in xaui_serdes_reset()
159 adapter_t *adap = mac->adapter; in t3_mac_init() local
162 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_); in t3_mac_init()
[all …]
H A Dcxgb_vsc7323.c51 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n) in t3_elmr_blk_write() argument
54 const struct mdio_ops *mo = adapter_info(adap)->mdio_ops; in t3_elmr_blk_write()
56 ELMR_LOCK(adap); in t3_elmr_blk_write()
57 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start); in t3_elmr_blk_write()
59 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_LO, in t3_elmr_blk_write()
62 ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_DATA_HI, in t3_elmr_blk_write()
65 ELMR_UNLOCK(adap); in t3_elmr_blk_write()
69 static int elmr_write(adapter_t *adap, int addr, u32 val) in elmr_write() argument
71 return t3_elmr_blk_write(adap, addr, &val, 1); in elmr_write()
74 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n) in t3_elmr_blk_read() argument
[all …]
H A Dcxgb_t3_hw.c120 static void t3_read_indirect(adapter_t *adap, unsigned int addr_reg, in t3_read_indirect() argument
125 t3_write_reg(adap, addr_reg, start_idx); in t3_read_indirect()
126 *vals++ = t3_read_reg(adap, data_reg); in t3_read_indirect()
148 adapter_t *adap = mc7->adapter; in t3_mc7_bd_read() local
162 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, in t3_mc7_bd_read()
164 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0); in t3_mc7_bd_read()
165 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP); in t3_mc7_bd_read()
167 val = t3_read_reg(adap, in t3_mc7_bd_read()
172 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1); in t3_mc7_bd_read()
174 val64 = t3_read_reg(adap, in t3_mc7_bd_read()
[all …]
H A Dcxgb_common.h643 #define adapter_info(adap) ((adap)->params.info) argument
645 static inline int uses_xaui(const adapter_t *adap) in uses_xaui() argument
647 return adapter_info(adap)->caps & SUPPORTED_AUI; in uses_xaui()
650 static inline int is_10G(const adapter_t *adap) in is_10G() argument
652 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; in is_10G()
655 static inline int is_offload(const adapter_t *adap) in is_offload() argument
657 return adap->params.offload; in is_offload()
660 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) in core_ticks_per_usec() argument
662 return adap->params.vpd.cclk / 1000; in core_ticks_per_usec()
665 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, in dack_ticks_to_usec() argument
[all …]
H A Dcxgb_vsc8211.c392 int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port) in t3_vsc8211_fifo_depth() argument
401 struct port_info *portinfo = adap2pinfo(adap, port); in t3_vsc8211_fifo_depth()
/src/sys/dev/cxgbe/common/
H A Dcommon.h555 static inline int is_offload(const struct adapter *adap) in is_offload() argument
557 return adap->params.offload; in is_offload()
560 static inline int is_ethoffload(const struct adapter *adap) in is_ethoffload() argument
562 return adap->params.ethoffload; in is_ethoffload()
565 static inline int is_hashfilter(const struct adapter *adap) in is_hashfilter() argument
567 return adap->params.hash_filter; in is_hashfilter()
570 static inline int is_ktls(const struct adapter *adap) in is_ktls() argument
572 return adap->cryptocaps & FW_CAPS_CONFIG_TLS_HW || in is_ktls()
573 adap->params.chipid == CHELSIO_T7; in is_ktls()
576 static inline int chip_id(const struct adapter *adap) in chip_id() argument
[all …]
H A Dt4_hw.c101 static int t7_wait_sram_done(struct adapter *adap, int reg, int result_reg, in t7_wait_sram_done() argument
105 u32 val = t4_read_reg(adap, reg); in t7_wait_sram_done()
110 *valp = t4_read_reg(adap, result_reg); in t7_wait_sram_done()
153 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, in t4_read_indirect() argument
158 t4_write_reg(adap, addr_reg, start_idx); in t4_read_indirect()
159 *vals++ = t4_read_reg(adap, data_reg); in t4_read_indirect()
176 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, in t4_write_indirect() argument
181 t4_write_reg(adap, addr_reg, start_idx++); in t4_write_indirect()
182 t4_write_reg(adap, data_reg, *vals++); in t4_write_indirect()
196 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) in t4_hw_pci_read_cfg4() argument
[all …]
/src/sys/dev/cxgbe/cudbg/
H A Dcudbg_flash_utils.c35 int write_flash(struct adapter *adap, u32 start_sec, void *data, u32 size);
36 int read_flash(struct adapter *adap, u32 start_sec , void *data, u32 size,
46 void set_sector_availability(struct adapter *adap, in set_sector_availability() argument
49 int start = t4_flash_loc_start(adap, FLASH_LOC_CUDBG, NULL); in set_sector_availability()
60 find_empty_sec(struct adapter *adap, struct cudbg_flash_sec_info *sec_info) in find_empty_sec() argument
64 int start = t4_flash_loc_start(adap, FLASH_LOC_CUDBG, &len); in find_empty_sec()
150 struct adapter *adap = cudbg_init->adap; in cudbg_write_flash() local
164 t4_flash_loc_start(adap, FLASH_LOC_CUDBG, &cudbg_max_size); in cudbg_write_flash()
202 sec = find_empty_sec(adap, sec_info); in cudbg_write_flash()
205 set_sector_availability(adap, sec_info, in cudbg_write_flash()
[all …]
H A Dcudbg_lib.c48 return (pdbg_init->adap->flags & FW_OK); in is_fw_attached()
74 struct adapter *padap = pdbg_init->adap; in read_sge_ctxt()
162 t4_flash_loc_start(cudbg_init->adap, FLASH_LOC_CUDBG, &cudbg_len); in wr_entity_to_flash()
214 struct adapter *padap = cudbg_init->adap; in cudbg_collect()
573 struct adapter *padap = pdbg_init->adap; in collect_rss()
608 struct adapter *padap = pdbg_init->adap; in collect_sw_state()
643 struct adapter *padap = pdbg_init->adap; in collect_ddp_stats()
677 struct adapter *padap = pdbg_init->adap; in collect_ulptx_la()
725 struct adapter *padap = pdbg_init->adap; in collect_ulprx_la()
757 struct adapter *padap = pdbg_init->adap; in collect_cpl_stats()
[all …]
H A Dcudbg.h352 void *adap; member
371 struct adapter *adap; /* Pointer to adapter structure member
/src/sys/dev/thunderbolt/
H A Drouter_var.h83 uint8_t adap; member
164 tb_config_adapter_read(struct router_softc *sc, u_int adap, u_int addr, in tb_config_adapter_read() argument
167 return (tb_config_read(sc, TB_CFG_CS_ADAPTER, adap, addr, dwlen, buf)); in tb_config_adapter_read()
178 tb_config_adapter_write(struct router_softc *sc, u_int adap, u_int addr, in tb_config_adapter_write() argument
181 return (tb_config_write(sc, TB_CFG_CS_ADAPTER, adap, addr, dwlen, buf)); in tb_config_adapter_write()
192 tb_config_path_read(struct router_softc *sc, u_int adap, u_int hopid, in tb_config_path_read() argument
195 return (tb_config_read(sc, TB_CFG_CS_PATH, adap, hopid * 2, in tb_config_path_read()
207 tb_config_path_write(struct router_softc *sc, u_int adap, u_int hopid, in tb_config_path_write() argument
210 return (tb_config_write(sc, TB_CFG_CS_PATH, adap, hopid * 2, in tb_config_path_write()
223 tb_config_counters_read(struct router_softc *sc, u_int adap, u_int set, in tb_config_counters_read() argument
[all …]
H A Drouter.c721 u_int ev, adap; in router_notify_intr() local
733 adap = GET_NOTIFY_ADAPTER(&event); in router_notify_intr()
736 event.route.hi, event.route.lo, adap, in router_notify_intr()
779 error = tb_config_read(sc, cap->space, cap->adap, current, 1, buf); in tb_config_next_cap()
794 tb_config_read(sc, cap->space, cap->adap, current, 2, buf); in tb_config_next_cap()
858 rcap.adap = 0; in tb_config_find_router_cap()
885 tb_config_find_adapter_cap(struct router_softc *sc, u_int adap, u_int cap, u_int *offset) in tb_config_find_adapter_cap() argument
896 error = tb_config_adapter_read(sc, adap, 0, 8, buf); in tb_config_find_adapter_cap()
904 rcap.adap = adap; in tb_config_find_adapter_cap()
/src/sys/dev/cxgb/
H A Dcxgb_adapter.h283 struct adapter *adap; member
420 #define ADAPTER_LOCK(adap) mtx_lock(&(adap)->lock); argument
421 #define ADAPTER_UNLOCK(adap) mtx_unlock(&(adap)->lock); argument
422 #define ADAPTER_LOCK_INIT(adap, name) mtx_init(&(adap)->lock, name, 0, MTX_DEF) argument
423 #define ADAPTER_LOCK_DEINIT(adap) mtx_destroy(&(adap)->lock) argument
424 #define ADAPTER_LOCK_ASSERT_NOTOWNED(adap) mtx_assert(&(adap)->lock, MA_NOTOWNED) argument
425 #define ADAPTER_LOCK_ASSERT_OWNED(adap) mtx_assert(&(adap)->lock, MA_OWNED) argument
472 adap2pinfo(struct adapter *adap, int idx) in adap2pinfo() argument
474 return &adap->port[idx]; in adap2pinfo()
483 void t3_os_phymod_changed(struct adapter *adap, int port_id);
[all …]
H A Dcxgb_sge.c428 t3_sge_init(adapter_t *adap, struct sge_params *p) in t3_sge_init() argument
441 if (adap->params.rev > 0) { in t3_sge_init()
442 if (!(adap->flags & (USING_MSIX | USING_MSI))) in t3_sge_init()
445 t3_write_reg(adap, A_SG_CONTROL, ctrl); in t3_sge_init()
446 t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) | in t3_sge_init()
448 t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10); in t3_sge_init()
449 t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) | in t3_sge_init()
450 V_TIMEOUT(200 * core_ticks_per_usec(adap))); in t3_sge_init()
451 t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH, in t3_sge_init()
452 adap->params.rev < T3_REV_C ? 1000 : 500); in t3_sge_init()
[all …]
H A Dcxgb_main.c1205 void t3_os_phymod_changed(struct adapter *adap, int port_id) in t3_os_phymod_changed() argument
1210 struct port_info *pi = &adap->port[port_id]; in t3_os_phymod_changed()
1270 await_mgmt_replies(struct adapter *adap, unsigned long init_cnt, in await_mgmt_replies() argument
1275 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) { in await_mgmt_replies()
1284 init_tp_parity(struct adapter *adap) in init_tp_parity() argument
1289 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts; in init_tp_parity()
1291 t3_tp_set_offload_mode(adap, 1); in init_tp_parity()
1303 t3_mgmt_tx(adap, m); in init_tp_parity()
1316 t3_mgmt_tx(adap, m); in init_tp_parity()
1329 t3_mgmt_tx(adap, m); in init_tp_parity()
[all …]
H A Dcxgb_osdep.h126 #define CH_ERR(adap, fmt, ...) log(LOG_ERR, fmt, ##__VA_ARGS__) argument
127 #define CH_WARN(adap, fmt, ...) log(LOG_WARNING, fmt, ##__VA_ARGS__) argument
128 #define CH_ALERT(adap, fmt, ...) log(LOG_ALERT, fmt, ##__VA_ARGS__) argument
/src/sys/dev/cxgbe/
H A Dosdep.h43 #define CH_ERR(adap, fmt, ...) log(LOG_ERR, "%s: " fmt, \ argument
44 device_get_nameunit((adap)->dev), ##__VA_ARGS__)
45 #define CH_WARN(adap, fmt, ...) log(LOG_WARNING, "%s: " fmt, \ argument
46 device_get_nameunit((adap)->dev), ##__VA_ARGS__)
47 #define CH_ALERT(adap, fmt, ...) log(LOG_ALERT, "%s: " fmt, \ argument
48 device_get_nameunit((adap)->dev), ##__VA_ARGS__)
49 #define CH_WARN_RATELIMIT(adap, fmt, ...) log(LOG_WARNING, "%s: " fmt, \ argument
50 device_get_nameunit((adap)->dev), ##__VA_ARGS__)
H A Dt4_iov.c377 struct adapter *adap; in t4iov_add_vf() local
385 adap = device_get_softc(sc->sc_main); in t4iov_add_vf()
391 if (begin_synchronized_op(adap, NULL, SLEEP_OK | INTR_OK, in t4iov_add_vf()
394 rc = -t4_set_vf_mac(adap, sc->pf, vfnum + 1, 1, ma); in t4iov_add_vf()
395 end_synchronized_op(adap, 0); in t4iov_add_vf()
415 if (begin_synchronized_op(adap, NULL, SLEEP_OK | INTR_OK, in t4iov_add_vf()
418 rc = t4_set_vlan_acl(adap, sc->pf, vfnum + 1, vlan); in t4iov_add_vf()
419 end_synchronized_op(adap, 0); in t4iov_add_vf()
/src/sys/dev/cxgbe/iw_cxgbe/
H A Dresource.c47 rdev->adap->vres.qp.start, in c4iw_init_qid_table()
48 rdev->adap->vres.qp.size, in c4iw_init_qid_table()
49 rdev->adap->vres.qp.size, 0)) { in c4iw_init_qid_table()
54 for (i = rdev->adap->vres.qp.start; in c4iw_init_qid_table()
55 i < rdev->adap->vres.qp.start + rdev->adap->vres.qp.size; i++) in c4iw_init_qid_table()
252 addr = t4_pblpool_alloc(rdev->adap, size); in c4iw_pblpool_alloc()
269 t4_pblpool_free(rdev->adap, addr, size); in c4iw_pblpool_free()
288 device_get_nameunit(rdev->adap->dev)); in c4iw_rqtpool_alloc()
313 rdev->adap->vres.rq.start, in c4iw_rqtpool_create()
314 rdev->adap->vres.rq.size, in c4iw_rqtpool_create()
H A Ddevice.c89 struct adapter *sc = rdev->adap; in c4iw_rdev_open()
161 rdev->status_page->wc_supported = rdev->adap->iwt.wc_en; in c4iw_rdev_open()
208 iwsc->rdev.adap = sc; in c4iw_alloc()
224 iwsc->rdev.hw_queue.t4_stat_len = iwsc->rdev.adap->params.sge.spg_len; in c4iw_alloc()
229 iwsc->rdev.bar2_kva = (void __iomem *)((u64)iwsc->rdev.adap->udbs_base); in c4iw_alloc()
230 iwsc->rdev.bar2_pa = vtophys(iwsc->rdev.adap->udbs_base); in c4iw_alloc()
231 iwsc->rdev.bar2_len = rman_get_size(iwsc->rdev.adap->udbs_res); in c4iw_alloc()
245 iwsc->avail_ird = iwsc->rdev.adap->params.max_ird_adapter; in c4iw_alloc()
H A Diw_cxgbe.h85 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
86 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
150 struct adapter *adap; member
176 return (int)(rdev->adap->vres.stag.size >> 5); in c4iw_num_stags()
181 if (rdev->adap->params.ulptx_memwrite_dsgl && use_dsgl) in t4_max_fr_depth()
182 return rdev->adap->params.dev_512sgl_mr ? T4_MAX_FR_FW_DSGL_DEPTH : T4_MAX_FR_DSGL_DEPTH; in t4_max_fr_depth()
210 struct adapter *sc = rdev->adap; in c4iw_wait_for_reply()
360 return min(dev->rdev.adap->params.max_ordird_qp, c4iw_max_read_depth); in cur_max_read_depth()
H A Dmem.c54 return (is_t5(dev->rdev.adap) && length >= 8*1024*1024*1024ULL); in mr_exceeds_hw_limits()
61 struct adapter *sc = rdev->adap; in _c4iw_write_mem_dma_aligned()
87 struct adapter *sc = rdev->adap; in _c4iw_write_mem_inline()
165 if (rdev->adap->params.ulptx_memwrite_dsgl && use_dsgl) { in write_adapter_mem()
205 stag_idx = t4_stag_alloc(rdev->adap, 1); in write_tpt_entry()
247 (rdev->adap->vres.stag.start >> 5), in write_tpt_entry()
251 t4_stag_free(rdev->adap, stag_idx, 1); in write_tpt_entry()
265 __func__, pbl_addr, rdev->adap->vres.pbl.start, pbl_size); in write_pbl()
H A Dprovider.c198 if (rdev->adap->iwt.wc_en && addr >= rdev->bar2_pa && in c4iw_mmap()
283 sc = dev->rdev.adap; in c4iw_query_gid()
296 struct adapter *sc = dev->rdev.adap; in c4iw_query_device()
346 sc = dev->rdev.adap; in c4iw_query_port()
404 struct adapter *sc = dev->rdev.adap; in c4iw_register_device()
517 dev->rdev.adap); in c4iw_unregister_device()
/src/contrib/ntp/libntp/lib/isc/win32/
H A Dinterfaceiter.c453 IP_ADAPTER_ADDRESSES *adap; in internal_current_GAA() local
459 adap = iter->ipaaCur; in internal_current_GAA()
468 iter->current.ifindex = adap->Ipv6IfIndex; in internal_current_GAA()
473 adap->FriendlyName, in internal_current_GAA()
480 if (IfOperStatusUp == adap->OperStatus) in internal_current_GAA()
482 if (IF_TYPE_PPP == adap->IfType) in internal_current_GAA()
484 else if (IF_TYPE_SOFTWARE_LOOPBACK == adap->IfType) in internal_current_GAA()
486 if ((IP_ADAPTER_NO_MULTICAST & adap->Flags) == 0) in internal_current_GAA()

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