| /src/sys/contrib/device-tree/Bindings/fsi/ |
| H A D | ibm,p9-occ.txt | 4 This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from
6 nodes. The OCC is not an FSI slave device itself, rather it is accessed
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| /src/sys/contrib/device-tree/Bindings/ |
| H A D | resource-names.txt | 2 normally accessed by index. However, some devices will have multiple
3 values which are more naturally accessed by name. Device nodes can
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| H A D | common-properties.txt | 15 know the peripheral always needs to be accessed in big endian (BE) mode.
18 peripheral always needs to be accessed in little endian (LE) mode.
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| /src/sys/contrib/device-tree/Bindings/hwmon/ |
| H A D | apm-xgene-hwmon.txt | 3 APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox.
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| /src/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-xgene-slimpro.txt | 3 An I2C controller accessed over the "SLIMpro" mailbox.
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| H A D | nvidia,tegra186-bpmp-i2c.txt | 7 accessed in such a fashion.
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| /src/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | snps,archs-intc.txt | 12 intc accessed via the special ARC AUX register interface, hence "reg" property
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| H A D | snps,arc700-intc.txt | 15 intc accessed via the special ARC AUX register interface, hence "reg" property
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| H A D | snps,archs-idu-intc.txt | 26 The interrupt controller is accessed via the special ARC AUX register
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| /src/crypto/openssl/doc/man3/ |
| H A D | RAND_get0_primary.pod | 25 shared DRBG instances which are accessed via the RAND API:
54 The I<public> and I<private> DRBG instance can be accessed safely, because
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| /src/sys/contrib/device-tree/src/openrisc/ |
| H A D | or1ksim.dts | 34 * OR1K PIC is built into CPU and accessed via special purpose
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| H A D | simple_smp.dts | 46 * OR1K PIC is built into CPU and accessed via special purpose
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| /src/sys/contrib/device-tree/Bindings/timer/ |
| H A D | csky,mptimer.txt | 6 regs is accessed by cpu co-processor 4 registers with mtcr/mfcr.
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| H A D | qcom,msm-timer.txt | 28 - cpu-offset : per-cpu offset used when the timer is accessed without the
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| /src/crypto/openssl/doc/man7/ |
| H A D | OSSL_PROVIDER-null.pod | 12 provider will not be accidentally accessed.
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| H A D | EVP_RAND.pod | 42 Multiple DRBG instances which are accessed only by a single thread provide
80 DRBG are created per thread and accessed through thread-local storage.
103 The <primary> DRBG is intended to be accessed concurrently for reseeding
108 instance of each per thread. So they can safely be accessed without
115 accessed and used by multiple threads.
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| /src/sys/contrib/device-tree/Bindings/arm/ |
| H A D | arm-dsu-pmu.txt | 8 The PMU is accessed via CPU system registers and has no MMIO component.
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| /src/tools/test/stress2/misc/ |
| H A D | mmap28.sh | 105 Truncating the mapped file triggers a panic when accessed beyond
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| /src/sys/contrib/device-tree/src/arm/intel/ixp/ |
| H A D | intel-ixp42x-linksys-wrv54g.dts | 81 * The PHYs are accessed over the external MDIO
206 * and PHY5 for WAN need to be accessed
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| /src/sys/contrib/device-tree/Bindings/pci/ |
| H A D | ti-pci.txt | 47 they are locally accessed within the DIF CS space
49 they are locally accessed within the DIF CS2 space
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| /src/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | hisilicon,hi3660-mailbox.txt | 5 processors, MCU, HIFI, etc. Each channel is unidirectional and accessed
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| /src/sys/contrib/device-tree/Bindings/bus/ |
| H A D | nvidia,tegra210-aconnect.txt | 21 All devices accessed via the ACONNNECT are described by child-nodes.
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| /src/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6ull-colibri-aster.dtsi | 66 * Following SODIMM Pins should not be accessed as GPIO on Aster board:
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| /src/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | amlogic,meson-mx-sdio.txt | 10 to be controlled. Only one slot can be accessed at a time.
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| /src/contrib/jemalloc/ |
| H A D | TUNING.md | 107 applications can explicitly allocate frequently accessed objects from a
121 for frequently accessed data, which reduces TLB misses significantly.
|