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Searched refs:ZeroInt (Results 1 – 5 of 5) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp5308 auto ZeroInt = B.buildConstant(S32, 0); in legalizeFSQRTF64() local
5313 auto ScaleUp = B.buildSelect(S32, Scaling, ScaleUpFactor, ZeroInt); in legalizeFSQRTF64()
5341 auto ScaleDown = B.buildSelect(S32, Scaling, ScaleDownFactor, ZeroInt); in legalizeFSQRTF64()
H A DSIISelLowering.cpp11097 SDValue ZeroInt = DAG.getConstant(0, DL, MVT::i32); in lowerFSQRTF64() local
11102 DAG.getNode(ISD::SELECT, DL, MVT::i32, Scaling, ScaleUpFactor, ZeroInt); in lowerFSQRTF64()
11132 DAG.getNode(ISD::SELECT, DL, MVT::i32, Scaling, ScaleDownFactor, ZeroInt); in lowerFSQRTF64()
/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp11197 SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); in expandFP_TO_INT_SAT() local
11201 return DAG.getSelect(dl, DstVT, IsNan, ZeroInt, FpToInt); in expandFP_TO_INT_SAT()
11232 SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); in expandFP_TO_INT_SAT() local
11234 return DAG.getSelect(dl, DstVT, IsNan, ZeroInt, Select); in expandFP_TO_INT_SAT()
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2942 SDValue ZeroInt = DAG.getConstant(0, DL, DstVT); in lowerFP_TO_INT_SAT() local
2943 return DAG.getSelectCC(DL, Src, Src, ZeroInt, FpToInt, in lowerFP_TO_INT_SAT()
15444 SDValue ZeroInt = DAG.getConstant(0, DL, DstVT); in performFP_TO_INT_SATCombine() local
15445 return DAG.getSelectCC(DL, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO); in performFP_TO_INT_SATCombine()
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp21386 SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); in LowerFP_TO_INT_SAT() local
21388 dl, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO); in LowerFP_TO_INT_SAT()
21425 SDValue ZeroInt = DAG.getConstant(0, dl, DstVT); in LowerFP_TO_INT_SAT() local
21427 dl, Src, Src, ZeroInt, Select, ISD::CondCode::SETUO); in LowerFP_TO_INT_SAT()