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Searched refs:XIN_OSC0_DIV (Results 1 – 5 of 5) sorted by relevance

/src/sys/dev/clk/rockchip/
H A Drk3568_pmucru.c163 GATE(XIN_OSC0_DIV, "xin_osc0_div", "xin_osc0_div_div", 0, 0),
/src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Drockchip,rk3528-cru.h384 #define XIN_OSC0_DIV 372 macro
H A Drockchip,rk3576-cru.h529 #define XIN_OSC0_DIV 511 macro
H A Drk3568-cru.h17 #define XIN_OSC0_DIV 4 macro
/src/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3528.dtsi428 <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,