| /src/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | aarch32.cpp | 225 : Wd{*reinterpret_cast<support::ulittle32_t *>(FixupPtr)} {} in WritableArmRelocation() 227 support::ulittle32_t &Wd; member 232 : Wd{*reinterpret_cast<const support::ulittle32_t *>(FixupPtr)} {} in ArmRelocation() 234 ArmRelocation(WritableArmRelocation &Writable) : Wd{Writable.Wd} {} in ArmRelocation() 236 const support::ulittle32_t &Wd; member 251 static_cast<uint32_t>(R.Wd), G.getEdgeKindName(Kind))); in makeUnexpectedOpcodeError() 261 template <EdgeKind_aarch32 K> static bool checkOpcodeArm(uint32_t Wd) { in checkOpcodeArm() argument 262 return (Wd & FixupInfo<K>::OpcodeMask) == FixupInfo<K>::Opcode; in checkOpcodeArm() 322 if (!Info.checkOpcode(R.Wd)) in checkOpcode() 354 uint32_t Wd = R.Wd & FixupInfo<Kind>::RegMask; in checkRegister() local [all …]
|
| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredNeoverse.td | 60 // MOV Wd, #0 66 // MOV Wd, WZR 68 // MOV Wd, Wn
|
| H A D | AArch64SchedA510.td | 577 (instregex "^(SQINC|SQDEC|UQINC|UQDEC)[BHWD]_[XW]Pi(Wd)?I")>;
|
| H A D | AArch64InstrInfo.td | 2753 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>; 2756 def : InstAlias<"mvn $Wd, $Wm$sh", 2757 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
|
| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 717 uint16_t Wd = im(2), Of = im(3); in evaluate() local 718 assert(Wd <= W0); in evaluate() 719 if (Wd == 0) in evaluate() 723 RegisterCell Pad = (Wd+Of > W0) ? rc(1).cat(eIMM(0, Wd+Of-W0)) : rc(1); in evaluate() 724 RegisterCell Ext = eXTR(Pad, Of, Wd+Of); in evaluate() 726 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1)); in evaluate() 728 return rr0(eZXT(RC, Wd), Outputs); in evaluate() 729 return rr0(eSXT(RC, Wd), Outputs); in evaluate() 733 uint16_t Wd = im(3), Of = im(4); in evaluate() local 734 assert(Wd < W0 && Of < W0); in evaluate() [all …]
|
| /src/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3243 Register Wd = MI.getOperand(0).getReg(); in emitINSERT_FW() local 3255 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) in emitINSERT_FW() 3279 Register Wd = MI.getOperand(0).getReg(); in emitINSERT_FD() local 3289 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) in emitINSERT_FD() 3325 Register Wd = MI.getOperand(0).getReg(); in emitINSERT_DF_VIDX() local 3417 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd) in emitINSERT_DF_VIDX() 3439 Register Wd = MI.getOperand(0).getReg(); in emitFILL_FW() local 3453 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); in emitFILL_FW() 3474 Register Wd = MI.getOperand(0).getReg(); in emitFILL_FD() local 3484 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); in emitFILL_FD() [all …]
|
| /src/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/ |
| H A D | aarch32.h | 182 bool (*checkOpcode)(uint32_t Wd) = nullptr;
|
| /src/contrib/netbsd-tests/usr.bin/netpgpverify/ |
| H A D | t_netpgpverify.sh | 650 Wd/uF+m5Z9S0da09xxgFH6U0lmHx+DphdmD7J4r5m9tx96g6JBmKmlSax3HZjgWr
|