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Searched refs:WR (Results 1 – 25 of 42) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp126 WriteRef &WR = RegisterMappings[RegID].first; in onInstructionExecuted() local
127 if (WR.getWriteState() == &WS) in onInstructionExecuted()
128 WR.notifyExecuted(CurrentCycle); in onInstructionExecuted()
364 WriteRef &WR = RegisterMappings[RegID].first; in removeRegisterWrite() local
365 if (WR.getWriteState() == &WS) in removeRegisterWrite()
366 WR.commit(); in removeRegisterWrite()
497 unsigned RegisterFile::getElapsedCyclesFromWriteBack(const WriteRef &WR) const { in getElapsedCyclesFromWriteBack()
498 assert(WR.hasKnownWriteBackCycle() && "Write hasn't been committed yet!"); in getElapsedCyclesFromWriteBack()
499 return CurrentCycle - WR.getWriteBackCycle(); in getElapsedCyclesFromWriteBack()
519 const WriteRef &WR = RegisterMappings[RegID].first; in collectWrites() local
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/src/sys/dev/iicbus/controller/qcom/
H A Dgeni_iic.c126 #define WR(sc, reg, val) bus_write_4((sc)->regs_res, reg, val) macro
182 WR(sc, GENI_M_IRQ_CLEAR, (1<<26)); in geniiic_intr()
188 WR(sc, GENI_M_IRQ_EN_CLEAR, (1<<0)); in geniiic_intr()
189 WR(sc, GENI_M_IRQ_EN_CLEAR, (1<<26)); in geniiic_intr()
190 WR(sc, GENI_M_IRQ_CLEAR, (1<<0)); in geniiic_intr()
200 WR(sc, GENI_M_IRQ_EN, 0); in geniiic_intr()
201 WR(sc, GENI_M_IRQ_CLEAR, m_status); in geniiic_intr()
214 WR(sc, GENI_DMA_TX_IRQ_EN_CLR, RD(sc, GENI_DMA_TX_IRQ_STAT)); in geniiic_intr()
215 WR(sc, GENI_DMA_TX_IRQ_CLR, RD(sc, GENI_DMA_TX_IRQ_STAT)); in geniiic_intr()
216 WR(sc, GENI_DMA_RX_IRQ_EN_CLR, RD(sc, GENI_DMA_RX_IRQ_STAT)); in geniiic_intr()
[all …]
/src/usr.bin/tail/
H A Dread.c90 WR(t + 1, len); in bytes()
98 WR(t + 1, len); in bytes()
102 WR(sp, tlen); in bytes()
107 WR(t + 1, len); in bytes()
109 WR(sp, tlen); in bytes()
113 WR(p, len); in bytes()
116 WR(sp, len); in bytes()
191 WR(llines[cnt].l, llines[cnt].len); in lines()
194 WR(llines[cnt].l, llines[cnt].len); in lines()
198 WR(llines[cnt].l, llines[cnt].len); in lines()
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H A Dmisc.c84 WR(mip->start + (startoff - mip->mapoff), n); in mapprint()
124 WR("\n", 1); in printfn()
125 WR("==> ", 4); in printfn()
126 WR(fn, strlen(fn)); in printfn()
127 WR(" <==\n", 5); in printfn()
H A Dreverse.c255 WR(p, llen + 1); in r_buf()
257 WR(p + 1, llen); in r_buf()
259 WR(p, 1); in r_buf()
267 WR(&tr->l, tr->len); in r_buf()
H A Dextern.h32 #define WR(p, size) do { \ macro
/src/contrib/ntp/libparse/
H A Dparsesolaris.c306 return putctl1(WR(q)->q_next, M_CTL, (mode == M_PARSE) ? MC_SERVICEIMM : in setup_stream()
350 WR(q)->q_ptr = q->q_ptr; in parseopen()
351 pprintf(DD_OPEN, "parse: OPEN - WQ parse area q=%x, q->q_ptr=%x\n", WR(q), WR(q)->q_ptr); in parseopen()
433 WR(q)->q_ptr = (caddr_t)NULL; in parseclose()
784 dq = WR(q); in init_linemon()
H A Dparsestreams.c458 return putctl1(WR(q)->q_next, M_CTL, (mode == M_PARSE) ? MC_SERVICEIMM : in setup_stream()
508 WR(q)->q_ptr = q->q_ptr; in parseopen()
588 WR(q)->q_ptr = (caddr_t)NULL; in parseclose()
934 dq = WR(q); in init_linemon()
/src/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a774e1-hihope-rzg2h-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774a1-hihope-rzg2m-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774a1-hihope-rzg2m-rev2-ex-idk-1110wr.dts4 * Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774b1-hihope-rzg2n-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dts4 * to an Advantech IDK-1110WR 10.1" LVDS panel
H A Dr8a774c0-ek874-idk-2121wr.dts4 * connected to an Advantech IDK-2121WR 21.5" LVDS panel
/src/sys/dev/cxgb/
H A Dcxgb_sge.c3160 uint32_t *WR, wr_hi, wr_lo, gen; in t3_dump_txq_eth() local
3202 WR = (uint32_t *)txd->flit; in t3_dump_txq_eth()
3203 wr_hi = ntohl(WR[0]); in t3_dump_txq_eth()
3204 wr_lo = ntohl(WR[1]); in t3_dump_txq_eth()
3211 WR[j], WR[j + 1], WR[j + 2], WR[j + 3]); in t3_dump_txq_eth()
3227 uint32_t *WR, wr_hi, wr_lo, gen; in t3_dump_txq_ctrl() local
3259 WR = (uint32_t *)txd->flit; in t3_dump_txq_ctrl()
3260 wr_hi = ntohl(WR[0]); in t3_dump_txq_ctrl()
3261 wr_lo = ntohl(WR[1]); in t3_dump_txq_ctrl()
3268 WR[j], WR[j + 1], WR[j + 2], WR[j + 3]); in t3_dump_txq_ctrl()
/src/crypto/openssl/test/recipes/15-test_ml_dsa_codecs_data/
H A Dprv-65-seed-priv.pem81 ytRfyTsnCMoq91zM5zT9GRxQCJ2tU5gv3a4CUx/5Ph8h/zlfwKEodO3wa2+WR+la
H A Dprv-65-bare-priv.pem81 a2+WR+lacyRYbHHf2R2QHWIYWBkP7NAMzRELusWflsuITDyTmUdIpW9BKDv8QfuJ
/src/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h295 unsigned getElapsedCyclesFromWriteBack(const WriteRef &WR) const;
/src/contrib/llvm-project/llvm/lib/Object/
H A DWindowsResource.cpp328 Error WindowsResourceParser::parse(WindowsResource *WR, in parse() argument
330 auto EntryOrErr = WR->getHeadEntry(); in parse()
348 InputFilenames.push_back(std::string(WR->getFileName())); in parse()
357 Entry, InputFilenames[Node->Origin], WR->getFileName())); in parse()
/src/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp913 for (Record *WR : ProcModel.WriteResDefs) { in FindWriteResources()
914 if (!WR->isSubClassOf("WriteRes")) in FindWriteResources()
916 Record *WRDef = WR->getValueAsDef("WriteType"); in FindWriteResources()
919 PrintFatalError(WR->getLoc(), "Resources are defined for both " in FindWriteResources()
923 ResDef = WR; in FindWriteResources()
/src/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DSValBuilder.cpp1081 const auto WR = RTy.getBitWidth(); in simplifySymbolCast() local
1085 if (((WT > WR) && (UR || !UT)) || ((WT == WR) && (UT == UR))) in simplifySymbolCast()
/src/contrib/llvm-project/llvm/include/llvm/Object/
H A DWindowsResource.h157 Error parse(WindowsResource *WR, std::vector<std::string> &Duplicates);
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp794 uint16_t WR = W0; in evaluate() local
796 assert(WR == 64 && WP == 8); in evaluate()
798 RegisterCell RC(WR); in evaluate()
/src/contrib/llvm-project/llvm/lib/Analysis/
H A DMemorySSA.cpp862 UpwardsWalkResult WR = walkToPhiOrClobber(Paths[Paused]); in tryOptimizePhi() local
863 if (WR.IsKnownClobber) in tryOptimizePhi()
864 Clobbers.push_back({WR.Result, Paused}); in tryOptimizePhi()
867 DefChainEnd = WR.Result; in tryOptimizePhi()
/src/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp1904 for (Record *WR : WRDefs) { in collectProcResources()
1905 Record *ModelDef = WR->getValueAsDef("SchedModel"); in collectProcResources()
1906 addWriteRes(WR, getProcModel(ModelDef).Index); in collectProcResources()

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