Searched refs:VectorList (Results 1 – 5 of 5) sorted by relevance
| /src/contrib/llvm-project/clang/utils/TableGen/ |
| H A D | ClangOpenCLBuiltinEmitter.cpp | 267 std::vector<int64_t> &VectorList) const; 887 std::vector<int64_t> VectorList = in EmitQualTypeFinder() local 889 OS << " QT.reserve(" << VectorList.size() * BaseTypes.size() << ");\n" in EmitQualTypeFinder() 890 << " for (unsigned I = 0; I < " << VectorList.size() << "; I++) {\n" in EmitQualTypeFinder() 1042 std::vector<int64_t> &VectorList) const { in getTypeLists() 1046 VectorList = in getTypeLists() 1063 getTypeLists(PossibleGenType, Flags, TypeList, VectorList); in getTypeLists() 1070 VectorList.push_back(Type->getValueAsInt("VecWidth")); in getTypeLists() 1083 std::vector<int64_t> VectorList; in expandTypesInSignature() local 1086 getTypeLists(Arg, Flags, TypeList, VectorList); in expandTypesInSignature() [all …]
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 951 struct VectorListOp VectorList; member 2052 return Kind == k_VectorList && !VectorList.isDoubleSpaced; in isSingleSpacedVectorList() 2056 return Kind == k_VectorList && VectorList.isDoubleSpaced; in isDoubleSpacedVectorList() 2064 return VectorList.Count == 1; in isVecListOneD() 2068 return isSingleSpacedVectorList() && VectorList.Count == 2 && in isVecListTwoMQ() 2070 VectorList.RegNum); in isVecListTwoMQ() 2080 .contains(VectorList.RegNum)); in isVecListDPair() 2085 return VectorList.Count == 3; in isVecListThreeD() 2090 return VectorList.Count == 4; in isVecListFourD() 2097 .contains(VectorList.RegNum)); in isVecListDPairSpaced() [all …]
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 502 struct VectorListOp VectorList; member 562 VectorList = o.VectorList; in AArch64Operand() 693 return VectorList.RegNum; in getVectorListStart() 698 return VectorList.Count; in getVectorListCount() 703 return VectorList.Stride; in getVectorListStride() 1423 return Kind == k_VectorList && VectorList.Count == NumRegs && in isImplicitlyTypedVectorList() 1424 VectorList.NumElements == 0 && in isImplicitlyTypedVectorList() 1425 VectorList.RegisterKind == VectorKind; in isImplicitlyTypedVectorList() 1433 if (VectorList.Count != NumRegs) in isTypedVectorList() 1435 if (VectorList.RegisterKind != VectorKind) in isTypedVectorList() [all …]
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 600 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> { 701 defm VecListOne : VectorList<1, FPR64, FPR128>; 702 defm VecListTwo : VectorList<2, DD, QQ>; 703 defm VecListThree : VectorList<3, DDD, QQQ>; 704 defm VecListFour : VectorList<4, DDDD, QQQQ>;
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| /src/contrib/llvm-project/clang/lib/Sema/ |
| H A D | OpenCLBuiltins.td | 272 // For example, if TypeList = <int, float> and VectorList = <1, 2, 4>, then it 298 IntList VectorList = _VectorList; 299 // The VecWidth field is ignored for GenericTypes. Use VectorList instead.
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