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Searched refs:Vec2 (Results 1 – 7 of 7) sorted by relevance

/src/contrib/llvm-project/clang/lib/AST/
H A DASTStructuralEquivalence.cpp957 const auto *Vec2 = cast<DependentSizedExtVectorType>(T2); in IsStructurallyEquivalent() local
959 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
962 Vec2->getElementType())) in IsStructurallyEquivalent()
969 const auto *Vec2 = cast<DependentVectorType>(T2); in IsStructurallyEquivalent() local
970 if (Vec1->getVectorKind() != Vec2->getVectorKind()) in IsStructurallyEquivalent()
973 Vec2->getSizeExpr())) in IsStructurallyEquivalent()
976 Vec2->getElementType())) in IsStructurallyEquivalent()
984 const auto *Vec2 = cast<VectorType>(T2); in IsStructurallyEquivalent() local
986 Vec2->getElementType())) in IsStructurallyEquivalent()
988 if (Vec1->getNumElements() != Vec2->getNumElements()) in IsStructurallyEquivalent()
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H A DExprConstant.cpp11091 const Expr *Vec2 = E->getExpr(1); in VisitShuffleVectorExpr() local
11092 if (!EvaluateAsRValue(Info, Vec2, VecVal2)) in VisitShuffleVectorExpr()
/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp1914 SDValue Vec2; in ExpandBVWithShuffles() local
1916 Vec2 = IntermedVals[1].first; in ExpandBVWithShuffles()
1918 Vec2 = DAG.getUNDEF(VT); in ExpandBVWithShuffles()
1927 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBVWithShuffles()
2029 SDValue Vec2; in ExpandBUILD_VECTOR() local
2031 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); in ExpandBUILD_VECTOR()
2033 Vec2 = DAG.getUNDEF(VT); in ExpandBUILD_VECTOR()
2036 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec); in ExpandBUILD_VECTOR()
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrMMA.td1078 dag Vec2 = (v4i32 (EXTRACT_SUBREG Pair1, sub_vsx0));
1094 Extracts.Vec2>;
/src/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp566 Value *Vec2 = nullptr; in isFixedVectorShuffle() local
611 } else if (!Vec2 || Vec2 == Vec) { in isFixedVectorShuffle()
612 Vec2 = Vec; in isFixedVectorShuffle()
628 if (CommonShuffleMode == Select && Vec2) in isFixedVectorShuffle()
632 return Vec2 ? TargetTransformInfo::SK_PermuteTwoSrc in isFixedVectorShuffle()
12581 Value *Vec2 = nullptr; in processBuildVector() local
12602 assert((!Vec2 || Vec2 == VecOp) && in processBuildVector()
12604 Vec2 = VecOp; in processBuildVector()
12608 if (Vec2) { in processBuildVector()
12611 isGuaranteedNotToBePoison(Vec1) && isGuaranteedNotToBePoison(Vec2); in processBuildVector()
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/src/contrib/llvm-project/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp5393 Value *Vec1, *Vec2, *Mask; in parseFunctionBody() local
5398 Vec2, CurBB)) in parseFunctionBody()
5404 if (!Vec1->getType()->isVectorTy() || !Vec2->getType()->isVectorTy()) in parseFunctionBody()
5407 I = new ShuffleVectorInst(Vec1, Vec2, Mask); in parseFunctionBody()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp14463 SDValue Vec2 = Op2.getOperand(0); in performFMACombine() local
14488 if (Vec1 == Vec2 || Vec3 == Vec4) in performFMACombine()
14491 if (Vec1.getValueType() != MVT::v2f16 || Vec2.getValueType() != MVT::v2f16) in performFMACombine()
14494 if ((Vec1 == Vec3 && Vec2 == Vec4) || in performFMACombine()
14495 (Vec1 == Vec4 && Vec2 == Vec3)) { in performFMACombine()
14496 return DAG.getNode(AMDGPUISD::FDOT2, SL, MVT::f32, Vec1, Vec2, FMAAcc, in performFMACombine()