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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoMMA.td19 // ACC - One of the 8 512-bit VSX accumulators.
25 // UACC - One of the 8 512-bit VSX accumulators prior to being primed.
88 // Placing Altivec registers first and allocate the rest as underlying VSX
91 // paired VSX registers.
H A DPPCInstrVSX.td1 //===- PPCInstrVSX.td - The PowerPC VSX Extension --*- tablegen -*-===//
9 // This file describes the VSX extension to the PowerPC instruction set.
14 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
139 //--------------------- VSX-specific instruction formats ---------------------//
140 // By default, all VSX instructions are to be selected over their Altivec
283 // VSX instructions require the VSX feature, they are to be selected over
1084 // The following VSX instructions were introduced in Power ISA 2.07
1109 // VSX scalar loads introduced in ISA 2.07
[all …]
H A DPPCRegisterInfo.td74 // registers (used by VSX).
88 // VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
96 // VSXReg - One of the VSX registers in the range vs32-vs63 with numbering
195 // VSX registers
202 // Dummy VSX registers, this defines string: "vs32"-"vs63", and is only used for
205 def VSX#Index : VSXReg<Index, "vs"#Index>;
425 // VSX register classes (the allocation order mirrors that of the corresponding
433 // Register classes for the 64-bit "scalar" VSX subregisters.
447 // Register class for single precision scalars in VSX registers
H A DPPCGenRegisterBankInfo.def25 // 4: 128-bit vector (VSX, Altivec)
H A DPPCScheduleP8.td57 // Two issue ports shared by 2 DFP/2 VSX/2 VMX/1 CY/1 DFP operations.
71 // Two issue ports shared by two floating-point, two VSX, two VMX, one crypto,
H A DPPCInstrAltivec.td14 // ** For POWER8 Little Endian, the VSX swap optimization relies on knowing **
15 // ** which VMX and VSX instructions are lane-sensitive and which are not. **
23 // ** When adding new VMX and VSX instructions, please consider whether they **
1320 // VSX equivalents. We need to fix this up at some point. Two possible
1322 // 1. Disable Altivec patterns that compete with VSX patterns using the
1323 // !HasVSX predicate. This essentially favours VSX over Altivec, in
1324 // hopes of reducing register pressure (larger register set using VSX
1328 // if we find situations where Altivec is really preferred over VSX.
H A DREADME_P9.txt173 VSX:
311 register. "XSCMPUDP" write to CR field, xscmp*dp write to VSX register
H A DPPC.td152 "Enable VSX instructions",
507 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
H A DPPCInstrP10.td2100 // Store element 0 of a VSX register to memory
2113 // Load element 0 of a VSX register to memory
2267 // Anonymous patterns to select prefixed VSX loads and stores.
H A DPPCInstrFormats.td1081 // XX*-Form (VSX)
H A DPPCInstrInfo.td276 // Move 2 i64 values into a VSX register
/src/contrib/llvm-project/clang/include/clang/Basic/
H A DPPCTypes.def18 // PPC_VECTOR_VSX_TYPE(Name, Id, Size) - A PPC VSX vector type of a given
H A DBuiltinsPPC.def715 // VSX built-ins.
H A DDiagnosticSemaKinds.td297 "use of 'double' with '__vector' requires VSX support to be enabled "
300 "use of '__int128' with '__vector bool' requires VSX support enabled (on "
306 "use of 'long long' with '__vector' requires VSX support (available on "
/src/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h18 (offsetof(VSX, regname) + sizeof(GPR) + sizeof(FPR) + sizeof(VMX))
458 } VSX; typedef
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsPowerPC.td248 /// PowerPC_VSX_Intrinsic - Base class for all VSX intrinsics.
343 // PowerPC VSX Intrinsic Class Definitions.
1284 // PowerPC VSX Intrinsic Definitions.
1511 // P10 VSX Vector permute extended.
1518 // P10 VSX Vector Blend Variable.