Searched refs:VLSHR (Results 1 – 4 of 4) sorted by relevance
225 VLSHR, enumerator
2338 case AArch64ISD::VLSHR: { in computeKnownBitsForTargetNode()2646 MAKE_CASE(AArch64ISD::VLSHR) in getTargetNodeName()13709 (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR || in tryLowerToSLI()13716 (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR || in tryLowerToSLI()13725 bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR || in tryLowerToSLI()14935 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; in LowerVectorSRA_SRL_SHL()19439 if (Shr.getOpcode() != AArch64ISD::VLSHR) in performConcatVectorsCombine()19479 DAG.getNode(AArch64ISD::VLSHR, dl, BVT, Add, N0.getOperand(1)); in performConcatVectorsCombine()20876 : AArch64ISD::VLSHR; in tryCombineShiftImm()22379 N->getOpcode() == AArch64ISD::VLSHR); in performVectorShiftCombine()[all …]
178 if (N.getOpcode() != AArch64ISD::VLSHR) in SelectRoundingVLShr()4539 N1->getOpcode() != AArch64ISD::VLSHR) in trySelectXAR()
771 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;