| /src/crypto/openssl/crypto/aes/asm/ |
| H A D | aes-riscv64-zvkned.pl | 63 $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
885 @{[vaeskf1_vi $V19, $V18, 9]} # v19 <- rk10 (w[36,39])
886 @{[vaeskf1_vi $V20, $V19, 10]} # v20 <- rk11 (w[40,43])
907 @{[vse32_v $V19, $KEYP]}
944 @{[vmv_v_v $V19, $V17]}
945 @{[vaeskf2_vi $V19, $V18, 9]}
947 @{[vaeskf2_vi $V20, $V19, 10]}
948 @{[vmv_v_v $V21, $V19]}
975 @{[vse32_v $V19, $KEYP]}
1054 @{[vle32_v $V19, $KEYP]}
[all …]
|
| H A D | aes-riscv64-zvkb-zvkned.pl | 76 $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
|
| H A D | aes-riscv64-zvbb-zvkg-zvkned.pl | 78 $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
|
| /src/crypto/openssl/crypto/sha/asm/ |
| H A D | sha256-riscv64-zvkb-zvknha_or_zvknhb.pl | 65 $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
95 @{[vle32_v $V19, $KT]}
238 @{[vadd_vv $V5, $V19, $V2]}
|
| H A D | sha512-riscv64-zvkb-zvknhb.pl | 65 $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
|
| /src/crypto/openssl/crypto/chacha/asm/ |
| H A D | chacha-riscv64-v-zbb.pl | 93 $V11, $V12, $V13, $V14, $V15, $V16, $V17, $V18, $V19, $V20, $V21,
406 @{[vxor_vv $V19, $V19, $V3]}
|
| /src/crypto/openssl/crypto/sm3/asm/ |
| H A D | sm3-riscv64-zvksh.pl | 69 $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
|
| /src/sys/contrib/device-tree/src/arm64/ti/ |
| H A D | k3-am642-evm-nand.dtso | 33 AM64X_IOPAD(0x005c, PIN_INPUT, 0) /* (V19) GPMC0_AD8 */
|
| H A D | k3-am62a7-sk.dts | 278 AM62AX_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V19) VOUT0_DATA8 */
|
| H A D | k3-am642-tqma64xxl-mbax4xxl.dts | 762 /* (V19) GPMC0_AD8.GPIO0_23 - WIFI-BT_EN */
|
| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| H A D | SystemZMCTargetDesc.cpp | 111 SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
|
| /src/crypto/openssl/crypto/modes/asm/ |
| H A D | aes-gcm-riscv64-zvkb-zvkg-zvkned.pl | 91 $V16, $V17, $V18, $V19, $V20, $V21, $V22, $V23,
|
| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 82 V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27, in getCallerSavedRegs()
|
| H A D | HexagonRegisterInfo.td | 241 def W9 : Rd<18, "v19:18", [V18, V19, VF9]>, DwarfRegNum<[117]>;
261 def WR9 : Rd<19, "v18:19", [V18, V19, VFR9]>, DwarfRegNum<[170]>;
|
| /src/sys/contrib/edk2/Include/Protocol/ |
| H A D | DebugSupport.h | 582 UINT64 V19[2]; member
|
| /src/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZCallingConv.td | 81 CCIfFixed<CCAssignToReg<[V16, V17, V18, V19, V20, V21]>>>>,
|
| /src/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 101 VE::V16, VE::V17, VE::V18, VE::V19, VE::V20, VE::V21, VE::V22, VE::V23,
|
| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 591 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19, in DecodeHvxVRRegisterClass()
|
| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.td | 422 V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
|
| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 18904 RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19,
20825 .Case("{v19}", RISCV::V19) in getRegForInlineAsmConstraint()
|