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Searched refs:UART4 (Results 1 – 23 of 23) sorted by relevance

/src/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-phygate-tauri-l-rs232-rs232.dtso38 /* UART4 - RS232 */
H A Dimx8mm-phygate-tauri-l-rs232-rs485.dtso39 /* UART4 - RS485 */
H A Dimx8-apalis-eval.dtsi77 /* Apalis UART4 */
H A Dimx8-apalis-ixora-v1.1.dtsi152 /* Apalis UART4 */
H A Dimx8-apalis-ixora-v1.2.dtsi201 /* Apalis UART4 */
H A Dimx8mm-data-modul-edm-sbc.dts978 /* UART4 is reserved for CM and RDC blocks CA access to UART4. */
H A Dimx8-apalis-v1.1.dtsi496 /* Apalis UART4 */
1248 /* Apalis UART4 */
/src/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dstm32mp1-clks.h33 #define UART4 20 macro
/src/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp15xx-dhcom-drc02.dtsi129 * however the STM32MP1 pinmux cannot map them to UART4 .
H A Dstm32f429.dtsi329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
/src/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra30-apalis-eval.dts77 /* Apalis UART4 */
H A Dtegra124-apalis-v1.2-eval.dts71 /* Apalis UART4 */
H A Dtegra124-apalis-eval.dts70 /* Apalis UART4 */
H A Dtegra30-apalis-v1.1-eval.dts78 /* Apalis UART4 */
H A Dtegra30-apalis.dtsi542 /* Apalis UART4 */
H A Dtegra30-apalis-v1.1.dtsi543 /* Apalis UART4 */
H A Dtegra124-apalis.dtsi687 /* Apalis UART4 */
H A Dtegra124-apalis-v1.2.dtsi690 /* Apalis UART4 */
/src/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-sr-som-brcm.dtsi123 /* UART4 - Connected to optional BRCM Wifi/BT/FM */
H A Dimx6qdl-sr-som-ti.dtsi130 /* UART4 - Connected to optional TI Wi-Fi/BT/FM */
H A Dimx6ull-phytec-tauri.dtsi253 /* UART4 * RS485 */
/src/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3588-friendlyelec-cm3588-nas.dts635 /* Shared with UART4, UART7 and PWM10 */
/src/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am642-tqma64xxl-mbax4xxl.dts846 /* Control GPIOs for IOT Module connected to UART4 */