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Searched refs:TargetSU (Results 1 – 6 of 6) sorted by relevance

/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DScheduleDAG.cpp601 const SUnit &TargetSU, in GetSubGraph() argument
605 int UpperBound = Node2Index[TargetSU.NodeNum]; in GetSubGraph()
654 WorkList.push_back(&TargetSU); in GetSubGraph()
706 bool ScheduleDAGTopologicalSort::WillCreateCycle(SUnit *TargetSU, SUnit *SU) { in WillCreateCycle() argument
709 if (IsReachable(SU, TargetSU)) in WillCreateCycle()
711 for (const SDep &PredDep : TargetSU->Preds) in WillCreateCycle()
727 const SUnit *TargetSU) { in IsReachable() argument
728 assert(TargetSU != nullptr && "Invalid target SUnit"); in IsReachable()
734 LowerBound = Node2Index[TargetSU->NodeNum]; in IsReachable()
741 DFS(TargetSU, UpperBound, HasLoop); in IsReachable()
H A DMachinePipeliner.cpp1641 SUnit *TargetSU = D.getSUnit(); in swapAntiDependences() local
1647 TargetSU->addPred(Dep); in swapAntiDependences()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h279 bool IsReachable(SUnit *SU, SUnit *TargetSU) { in IsReachable() argument
280 return Topo.IsReachable(SU, TargetSU); in IsReachable()
H A DScheduleDAG.h770 std::vector<int> GetSubGraph(const SUnit &StartSU, const SUnit &TargetSU,
774 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
777 bool WillCreateCycle(SUnit *TargetSU, SUnit *SU);
/src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp211 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
212 return Topo.IsReachable(SU, TargetSU); in IsReachable()
217 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
218 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUIGroupLP.cpp959 Cache->begin(), Cache->end(), [&SU, &DAG](SUnit *TargetSU) { in apply() argument
960 return DAG->IsReachable(TargetSU, const_cast<SUnit *>(SU)); in apply()