| /src/crypto/openssl/crypto/rc4/asm/ |
| H A D | rc4-x86_64.pl | 166 my @TX=("%rax","%rbx");
180 xor $TX[1],$TX[1]
182 sub $XX[0],$TX[1]
184 movl ($dat,$XX[0],4),$TX[0]#d
189 and \$7,$TX[1]
192 sub $TX[1],$len
194 add $TX[0]#b,$YY#b
196 movl $TX[0]#d,($dat,$YY,4)
198 add $TY#b,$TX[0]#b
200 movl ($dat,$TX[0],4),$TY#d
[all …]
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| H A D | rc4-md5-x86_64.pl | 116 my @TX=("%rax","%rbx");
172 movl ($dat,$XX[0],4),$TX[0]#d
175 xor $TX[1],$TX[1]
178 sub $XX[0],$TX[1]
179 and \$`$MOD-1`,$TX[1]
181 sub $TX[1],$len
183 add $TX[0]#b,$YY#b
185 movl $TX[0]#d,($dat,$YY,4)
187 add $TY#b,$TX[0]#b
189 movl ($dat,$TX[0],4),$TY#d
[all …]
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| H A D | rc4-c64xplus.pl | 31 ($KEYB,$YY,$TX,$tx,$SUM,$dat)=map("B$_",(5,7,8,9,1,2));
60 LDBU *${KEYA}[$XX],$TX
65 || ADD4 $TX,$YY,$YY
73 STB $TX,*${KEYB}[$YY]
74 ||[B0] ADD4 $TX,$YY,$YY
77 ||[!B0] MVD $tx,$TX
78 ADD4 $TY,$TX,$SUM ; [0,0] $TX is not replaced by $tx yet!
91 || SUB4 $YY,$TX,$YY
116 || MVK 0,$TX
117 STH $TX,*${KEY}++ ; key->x=key->y=0
[all …]
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| H A D | rc4-s390x.pl | 65 @TX=("%r8","%r9");
86 llgc $TX[0],2($XX[0],$key)
95 la $YY,0($YY,$TX[0]) # $i
109 stc $TX[0],2($YY,$key)
110 llgc $TX[1],2($XX[1],$key)
114 la $TX[1],0($TX[0])
116 la $TY,0($TY,$TX[0])
119 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
123 lg $TX[1],0($inp)
127 xgr $acc,$TX[1]
[all …]
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| H A D | rc4-parisc.pl | 88 @TX=("%r21","%r22");
108 $LDX $XX[1]($key),$TX[1]
110 $ST $TX[0],0($ix)
112 copy $TX[0],$TX[1] ; move
115 addl $TX[0],$TY,$TY
116 addl $TX[1],$YY,$YY
120 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers
130 $ST $TX[0],0($iy)
133 addl $TX[0],$TY,$TY
138 $LDX $XX[0]($key),$TX[0]
[all …]
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| /src/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | sc7280-herobrine-villager-r1.dtsi | 26 "TX SWR_ADC0", "ADC1_OUTPUT",
27 "TX SWR_ADC1", "ADC2_OUTPUT",
28 "TX SWR_ADC2", "ADC3_OUTPUT",
29 "TX SWR_DMIC0", "DMIC1_OUTPUT",
30 "TX SWR_DMIC1", "DMIC2_OUTPUT",
31 "TX SWR_DMIC2", "DMIC3_OUTPUT",
32 "TX SWR_DMIC3", "DMIC4_OUTPUT",
33 "TX SWR_DMIC4", "DMIC5_OUTPUT",
34 "TX SWR_DMIC5", "DMIC6_OUTPUT",
35 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
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| H A D | sc7280-crd-r3.dts | 104 "TX SWR_ADC0", "ADC1_OUTPUT",
105 "TX SWR_ADC1", "ADC2_OUTPUT",
106 "TX SWR_ADC2", "ADC3_OUTPUT",
107 "TX SWR_DMIC0", "DMIC1_OUTPUT",
108 "TX SWR_DMIC1", "DMIC2_OUTPUT",
109 "TX SWR_DMIC2", "DMIC3_OUTPUT",
110 "TX SWR_DMIC3", "DMIC4_OUTPUT",
111 "TX SWR_DMIC4", "DMIC5_OUTPUT",
112 "TX SWR_DMIC5", "DMIC6_OUTPUT",
113 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
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| H A D | sc7280-herobrine-audio-wcd9385.dtsi | 23 "TX SWR_ADC0", "ADC1_OUTPUT",
24 "TX SWR_ADC1", "ADC2_OUTPUT",
25 "TX SWR_ADC2", "ADC3_OUTPUT",
26 "TX SWR_DMIC0", "DMIC1_OUTPUT",
27 "TX SWR_DMIC1", "DMIC2_OUTPUT",
28 "TX SWR_DMIC2", "DMIC3_OUTPUT",
29 "TX SWR_DMIC3", "DMIC4_OUTPUT",
30 "TX SWR_DMIC4", "DMIC5_OUTPUT",
31 "TX SWR_DMIC5", "DMIC6_OUTPUT",
32 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
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| H A D | sc7280-idp.dtsi | 104 "TX SWR_ADC0", "ADC1_OUTPUT",
105 "TX SWR_ADC1", "ADC2_OUTPUT",
106 "TX SWR_ADC2", "ADC3_OUTPUT",
107 "TX SWR_DMIC0", "DMIC1_OUTPUT",
108 "TX SWR_DMIC1", "DMIC2_OUTPUT",
109 "TX SWR_DMIC2", "DMIC3_OUTPUT",
110 "TX SWR_DMIC3", "DMIC4_OUTPUT",
111 "TX SWR_DMIC4", "DMIC5_OUTPUT",
112 "TX SWR_DMIC5", "DMIC6_OUTPUT",
113 "TX SWR_DMIC6", "DMIC7_OUTPUT",
[all …]
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| H A D | sm8250-mtp.dts | 669 "TX SWR_ADC0", "ADC1_OUTPUT",
670 "TX SWR_ADC1", "ADC2_OUTPUT",
671 "TX SWR_ADC2", "ADC3_OUTPUT",
672 "TX SWR_ADC3", "ADC4_OUTPUT",
673 "TX SWR_DMIC0", "DMIC1_OUTPUT",
674 "TX SWR_DMIC1", "DMIC2_OUTPUT",
675 "TX SWR_DMIC2", "DMIC3_OUTPUT",
676 "TX SWR_DMIC3", "DMIC4_OUTPUT",
677 "TX SWR_DMIC4", "DMIC5_OUTPUT",
678 "TX SWR_DMIC5", "DMIC6_OUTPUT",
[all …]
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| /src/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | renesas,dw-hdmi.txt | 1 Renesas Gen3 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
15 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16 - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
17 - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
18 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
19 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
20 - "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
21 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
[all …]
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| H A D | dw_hdmi.txt | 1 Synopsys DesignWare HDMI TX Encoder
5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
19 - interrupts: Reference to the DWC HDMI TX interrupt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
30 - ports: The connectivity of the DWC HDMI TX with the rest of the system is
|
| /src/sys/contrib/device-tree/Bindings/net/ |
| H A D | micrel-ksz90x1.txt | 51 - txen-skew-ps : Skew control of TX CTL pad
56 - txd0-skew-ps : Skew control of TX data 0 pad
57 - txd1-skew-ps : Skew control of TX data 1 pad
58 - txd2-skew-ps : Skew control of TX data 2 pad
59 - txd3-skew-ps : Skew control of TX data 3 pad
138 - txc-skew-ps : Skew control of TX clock pad
143 - txen-skew-ps : Skew control of TX CTL pad
148 - txd0-skew-ps : Skew control of TX data 0 pad
149 - txd1-skew-ps : Skew control of TX data 1 pad
150 - txd2-skew-ps : Skew control of TX data 2 pad
[all …]
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| H A D | xilinx_axienet.txt | 7 segments of memory for buffering TX and RX, as well as the capability of
8 offloading TX/RX checksum calculation off the processor.
24 - interrupts : Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
26 specified, the TX/RX DMA interrupts should be on that node
38 - xlnx,txcsum : 0 or empty for disabling TX checksum offload,
39 1 to enable partial TX checksum offload,
40 2 to enable full TX checksum offload
66 device (DMA registers and DMA TX/RX interrupts) rather
|
| H A D | lantiq,xrx200-net.txt | 9 - interrupts : TX and RX DMA interrupts. Use interrupt-names "tx" for
10 : the TX interrupt and "rx" for the RX interrupt.
|
| /src/crypto/openssl/doc/designs/quic-design/ |
| H A D | quic-fc.md | 77 sent (for the TX side) or received (for the RX side). This represents the
100 - If the available credit is zero, the TX side is blocked due to a lack of
107 Connection-Level Flow Control - TX Side
110 TX side flow control is exceptionally simple. It can be modelled as the
113 ---> event: On TX (numBytes)
114 ---> event: On TX Window Updated (numBytes)
115 <--- event: On TX Blocked
116 Get TX Window() -> numBytes
118 The On TX event is passed to the state machine whenever we send a packet.
121 value is added to the TX-side SWM value. Note that this may be zero, though
[all …]
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| /src/sys/contrib/device-tree/Bindings/dma/ |
| H A D | ste-dma40.txt | 60 bidirectional, i.e. the same for RX and TX operations:
111 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
112 50: Hash Accelerator 1 TX
113 51: memcpy TX (to be used by the DMA driver for memcpy operations)
124 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
125 63: Hash Accelerator 0 TX
|
| /src/sys/contrib/device-tree/Bindings/sound/ |
| H A D | nvidia,tegra30-ahub.txt | 61 For TX CIFs, the numbers indicate the bit position within the AHUB routing
62 registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
|
| /src/sys/dev/qat/qat_common/ |
| H A D | adf_cfg_instance.c | 17 bundle->rings[i]->mode == TX) { in crypto_instance_init()
29 bundle->rings[i]->mode == TX) { in crypto_instance_init()
73 bundle->rings[i]->mode == TX) { in dc_instance_init()
105 bundle->rings[i]->mode == TX) { in asym_instance_init()
137 bundle->rings[i]->mode == TX) { in sym_instance_init()
|
| /src/sys/contrib/device-tree/src/arm64/amlogic/ |
| H A D | meson-gxbb-nanopi-k2.dts | 240 gpio-line-names = "UART TX", "UART RX", "Power Control", "Power Key In",
253 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
254 "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
289 "Bluetooth UART TX", "Bluetooth UART RX",
|
| H A D | meson-gxbb-odroidc2.dts | 283 gpio-line-names = "UART TX", "UART RX", "VCCK En", "TF 3V3/1V8 En",
296 "Eth RX D3", "Eth RGMII TX Clk", "Eth TX En",
297 "Eth TX D0", "Eth TX D1", "Eth TX D2", "Eth TX D3",
|
| /src/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | toshiba,tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
|
| H A D | tc358743.txt | 1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
|
| /src/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | hdmi.txt | 1 Freescale i.MX6 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
|
| /src/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | hisilicon,hi6220-mailbox.txt | 23 slot_id: Slot id used either for TX or RX
26 TX/RX interrupt to application processor,
36 flag" mode or IRQ generated mode to acknowledge a TX
|