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Searched refs:Subtarget (Results 1 – 25 of 310) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrPredicates.td35 def HasEGPR : Predicate<"Subtarget->hasEGPR()">;
36 def NoEGPR : Predicate<"!Subtarget->hasEGPR()">;
46 def HasNDD : Predicate<"Subtarget->hasNDD()">;
47 def NoNDD : Predicate<"!Subtarget->hasNDD()">;
48 def HasCF : Predicate<"Subtarget->hasCF()">;
49 def HasCMOV : Predicate<"Subtarget->canUseCMOV()">;
50 def NoCMOV : Predicate<"!Subtarget->canUseCMOV()">;
51 def HasNOPL : Predicate<"Subtarget->hasNOPL()">;
52 def HasMMX : Predicate<"Subtarget->hasMMX()">;
53 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">;
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H A DX86ISelLoweringCall.cpp71 const X86Subtarget &Subtarget) { in handleMaskRegisterForCallingConv() argument
86 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall)) in handleMaskRegisterForCallingConv()
89 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) { in handleMaskRegisterForCallingConv()
90 if (Subtarget.useAVX512Regs()) in handleMaskRegisterForCallingConv()
96 if (!isPowerOf2_32(NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) || in handleMaskRegisterForCallingConv()
107 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) { in getRegisterTypeForCallingConv()
113 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget); in getRegisterTypeForCallingConv()
123 if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() && in getRegisterTypeForCallingConv()
124 !Subtarget.hasX87()) in getRegisterTypeForCallingConv()
141 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) { in getNumRegistersForCallingConv()
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H A DX86SelectionDAGInfo.cpp62 const X86Subtarget &Subtarget = in EmitTargetCodeForMemset() local
69 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemset()
88 if (Subtarget.is64Bit() && Alignment >= Align(8)) { // QWORD aligned in EmitTargetCodeForMemset()
121 bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in EmitTargetCodeForMemset()
156 static SDValue emitRepmovs(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovs() argument
159 const bool Use64BitRegs = Subtarget.isTarget64BitLP64(); in emitRepmovs()
178 static SDValue emitRepmovsB(const X86Subtarget &Subtarget, SelectionDAG &DAG, in emitRepmovsB() argument
181 return emitRepmovs(Subtarget, DAG, dl, Chain, Dst, Src, in emitRepmovsB()
186 static MVT getOptimalRepmovsType(const X86Subtarget &Subtarget, in getOptimalRepmovsType() argument
199 return Subtarget.is64Bit() ? MVT::i64 : MVT::i32; in getOptimalRepmovsType()
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H A DX86ISelLowering.cpp129 : TargetLowering(TM), Subtarget(STI) { in X86TargetLowering()
130 bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); in X86TargetLowering()
147 if (Subtarget.isAtom()) in X86TargetLowering()
149 else if (Subtarget.is64Bit()) in X86TargetLowering()
153 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in X86TargetLowering()
158 if (Subtarget.hasSlowDivide32()) in X86TargetLowering()
160 if (Subtarget.hasSlowDivide64() && Subtarget.is64Bit()) in X86TargetLowering()
165 if (Subtarget.isTargetWindowsMSVC() || Subtarget.isTargetWindowsItanium()) { in X86TargetLowering()
184 if (Subtarget.canUseCMPXCHG16B()) in X86TargetLowering()
186 else if (Subtarget.canUseCMPXCHG8B()) in X86TargetLowering()
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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMPredicates.td9 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
11 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
12 def HasV5T : Predicate<"Subtarget->hasV5TOps()">,
14 def NoV5T : Predicate<"!Subtarget->hasV5TOps()">;
15 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
20 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
23 def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">,
26 def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">,
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H A DARMMachineFunctionInfo.cpp30 const ARMSubtarget *Subtarget) { in GetBranchTargetEnforcement() argument
31 if (!Subtarget->isMClass() || !Subtarget->hasV7Ops()) in GetBranchTargetEnforcement()
56 const ARMSubtarget *Subtarget) in ARMFunctionInfo() argument
57 : isThumb(Subtarget->isThumb()), hasThumb2(Subtarget->hasThumb2()), in ARMFunctionInfo()
60 BranchTargetEnforcement(GetBranchTargetEnforcement(F, Subtarget)) { in ARMFunctionInfo()
61 if (Subtarget->isMClass() && Subtarget->hasV7Ops()) in ARMFunctionInfo()
H A DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall() local
43 const ARMTargetLowering *TLI = Subtarget.getTargetLowering(); in EmitSpecializedLibcall()
141 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop() argument
161 ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold() && in shouldGenerateInlineTPLoop()
163 Subtarget.getMaxMemcpyTPInlineSizeThreshold()) in shouldGenerateInlineTPLoop()
172 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy() local
176 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
177 shouldGenerateInlineTPLoop(Subtarget, DAG, ConstantSize, Alignment, true)) in EmitTargetCodeForMemcpy()
191 if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold()) in EmitTargetCodeForMemcpy()
202 const unsigned MaxLoadsInLDM = Subtarget.isThumb1Only() ? 4 : 6; in EmitTargetCodeForMemcpy()
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/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp94 const MipsSubtarget &Subtarget = MF->getSubtarget<MipsSubtarget>(); in getCalleeSavedRegs() local
97 if (Subtarget.hasMips64()) in getCalleeSavedRegs()
98 return Subtarget.hasMips64r6() ? CSR_Interrupt_64R6_SaveList in getCalleeSavedRegs()
101 return Subtarget.hasMips32r6() ? CSR_Interrupt_32R6_SaveList in getCalleeSavedRegs()
105 if (Subtarget.isSingleFloat()) in getCalleeSavedRegs()
108 if (Subtarget.isABI_N64()) in getCalleeSavedRegs()
111 if (Subtarget.isABI_N32()) in getCalleeSavedRegs()
114 if (Subtarget.isFP64bit()) in getCalleeSavedRegs()
117 if (Subtarget.isFPXX()) in getCalleeSavedRegs()
126 const MipsSubtarget &Subtarget = MF.getSubtarget<MipsSubtarget>(); in getCallPreservedMask() local
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td23 // Subtarget Features (device properties)
963 // Subtarget Features (options and debugging)
1768 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS">,
1772 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1773 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS">,
1777 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1778 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
1779 "Subtarget->getGeneration() == AMDGPUSubtarget::GFX10">,
1783 Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
1784 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||"
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCLowerMASSVEntries.cpp54 static StringRef getCPUSuffix(const PPCSubtarget *Subtarget);
56 const PPCSubtarget *Subtarget);
59 const PPCSubtarget *Subtarget);
75 StringRef PPCLowerMASSVEntries::getCPUSuffix(const PPCSubtarget *Subtarget) { in getCPUSuffix() argument
77 if (!Subtarget) in getCPUSuffix()
80 if (Subtarget->isAIXABI() && Subtarget->hasP10Vector()) in getCPUSuffix()
82 if (Subtarget->hasP9Vector()) in getCPUSuffix()
84 if (Subtarget->hasP8Vector()) in getCPUSuffix()
86 if (Subtarget->isAIXABI()) in getCPUSuffix()
98 const PPCSubtarget *Subtarget) { in createMASSVFuncName() argument
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H A DPPCRegisterInfo.cpp186 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); in getCalleeSavedRegs() local
188 if (!TM.isPPC64() && Subtarget.isAIXABI()) in getCalleeSavedRegs()
190 if (Subtarget.hasVSX()) { in getCalleeSavedRegs()
191 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs()
193 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
197 if (Subtarget.hasAltivec()) { in getCalleeSavedRegs()
198 if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) in getCalleeSavedRegs()
213 !Subtarget.isUsingPCRelativeCalls(); in getCalleeSavedRegs()
217 if (Subtarget.isAIXABI()) in getCalleeSavedRegs()
220 if (Subtarget.pairedVectorMemops()) in getCalleeSavedRegs()
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H A DPPCFrameLowering.cpp85 Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)), in PPCFrameLowering()
86 TOCSaveOffset(computeTOCSaveOffset(Subtarget)), in PPCFrameLowering()
87 FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)), in PPCFrameLowering()
88 LinkageSize(computeLinkageSize(Subtarget)), in PPCFrameLowering()
89 BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)), in PPCFrameLowering()
90 CRSaveOffset(computeCRSaveOffset(Subtarget)) {} in PPCFrameLowering()
231 if (Subtarget.is64BitELFABI()) { in getCalleeSavedSpillSlots()
236 if (Subtarget.is32BitELFABI()) { in getCalleeSavedSpillSlots()
241 assert(Subtarget.isAIXABI() && "Unexpected ABI."); in getCalleeSavedSpillSlots()
243 if (Subtarget.isPPC64()) { in getCalleeSavedSpillSlots()
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H A DPPCISelLowering.cpp172 : TargetLowering(TM), Subtarget(STI) { in PPCTargetLowering()
179 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering()
188 if (!Subtarget.hasEFPU2()) in PPCTargetLowering()
213 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
243 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
259 if (Subtarget.useCRBits()) { in PPCTargetLowering()
262 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
336 if (Subtarget.isISA3_0()) { in PPCTargetLowering()
371 if (!Subtarget.hasSPE()) { in PPCTargetLowering()
376 if (Subtarget.hasVSX()) { in PPCTargetLowering()
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td78 def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
85 def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
93 def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
116 def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
129 def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
136 def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
144 def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
152 def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
163 def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
171 def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
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H A DRISCVISelLowering.cpp85 : TargetLowering(TM), Subtarget(STI) { in RISCVTargetLowering()
87 RISCVABI::ABI ABI = Subtarget.getTargetABI(); in RISCVTargetLowering()
91 !Subtarget.hasStdExtF()) { in RISCVTargetLowering()
95 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
97 !Subtarget.hasStdExtD()) { in RISCVTargetLowering()
101 ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32; in RISCVTargetLowering()
118 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering()
122 if (Subtarget.is64Bit() && RV64LegalI32) in RISCVTargetLowering()
125 if (Subtarget.hasStdExtZfhmin()) in RISCVTargetLowering()
127 if (Subtarget.hasStdExtZfbfmin()) in RISCVTargetLowering()
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp53 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg() local
55 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT, in assignArg()
57 *Subtarget.getTargetLowering(), RVVDispatcher)) in assignArg()
69 Subtarget(MIRBuilder.getMF().getSubtarget<RISCVSubtarget>()) {} in RISCVOutgoingValueHandler()
74 LLT p0 = LLT::pointer(0, Subtarget.getXLen()); in getStackAddress()
75 LLT sXLen = LLT::scalar(Subtarget.getXLen()); in getStackAddress()
170 const RISCVSubtarget &Subtarget; member
199 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>(); in assignArg() local
204 if (RISCVAssignFn(DL, Subtarget.getTargetABI(), ValNo, ValVT, LocVT, in assignArg()
206 *Subtarget.getTargetLowering(), RVVDispatcher)) in assignArg()
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/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyUtilities.cpp104 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFunctionTableSymbol() argument
111 bool is64 = Subtarget && Subtarget->getTargetTriple().isArch64Bit(); in getOrCreateFunctionTableSymbol()
118 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFunctionTableSymbol()
124 MCContext &Ctx, const WebAssemblySubtarget *Subtarget) { in getOrCreateFuncrefCallTableSymbol() argument
143 if (!(Subtarget && Subtarget->hasReferenceTypes())) in getOrCreateFuncrefCallTableSymbol()
187 const WebAssemblySubtarget *Subtarget) { in canLowerMultivalueReturn() argument
189 Subtarget->getTargetLowering()->getTargetMachine()); in canLowerMultivalueReturn()
190 return Subtarget->hasMultivalue() && TM.usesMultivalueABI(); in canLowerMultivalueReturn()
194 const WebAssemblySubtarget *Subtarget) { in canLowerReturn() argument
195 return ResultSize <= 1 || canLowerMultivalueReturn(Subtarget); in canLowerReturn()
/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRMCInstLower.cpp27 const AVRSubtarget &Subtarget) const { in lowerSymbolOperand()
46 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_LO8_GS in lowerSymbolOperand()
55 AVRMCExpr::create(Subtarget.hasEIJMPCALL() ? AVRMCExpr::VK_AVR_HI8_GS in lowerSymbolOperand()
70 auto &Subtarget = MI.getParent()->getParent()->getSubtarget<AVRSubtarget>(); in lowerInstruction() local
91 lowerSymbolOperand(MO, Printer.getSymbol(MO.getGlobal()), Subtarget); in lowerInstruction()
95 MO, Printer.GetExternalSymbolSymbol(MO.getSymbolName()), Subtarget); in lowerInstruction()
105 MO, Printer.GetBlockAddressSymbol(MO.getBlockAddress()), Subtarget); in lowerInstruction()
109 Subtarget); in lowerInstruction()
113 Subtarget); in lowerInstruction()
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DLeonPasses.cpp40 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
41 if (!Subtarget->insertNOPLoad()) in runOnMachineFunction()
44 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
79 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
80 if (!Subtarget->detectRoundChange()) in runOnMachineFunction()
129 Subtarget = &MF.getSubtarget<SparcSubtarget>(); in runOnMachineFunction()
130 if (!Subtarget->fixAllFDIVSQRT()) in runOnMachineFunction()
133 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in runOnMachineFunction()
H A DSparcRegisterInfo.cpp54 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getReservedRegs() local
65 if (!Subtarget.is64Bit()) in getReservedRegs()
80 if (ReserveAppRegisters || !Subtarget.is64Bit()) in getReservedRegs()
88 if (!Subtarget.isV9()) { in getReservedRegs()
117 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in getPointerRegClass() local
118 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; in getPointerRegClass()
183 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); in eliminateFrameIndex() local
192 if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { in eliminateFrameIndex()
194 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
206 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); in eliminateFrameIndex()
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PointerAuth.cpp44 const AArch64Subtarget *Subtarget = nullptr; member in __anon674d9b6f0111::AArch64PointerAuth
78 static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB, in BuildPACM() argument
81 const TargetInstrInfo *TII = Subtarget.getInstrInfo(); in BuildPACM()
94 if (MFnI.branchProtectionPAuthLR() && !Subtarget.hasPAuthLR()) in BuildPACM()
125 if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in signLR()
132 BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup); in signLR()
189 if (Subtarget->hasPAuth() && TerminatorIsCombinable && !NeedsWinCFI && in authenticateLR()
191 if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in authenticateLR()
199 BuildPACM(*Subtarget, MBB, TI, DL, MachineInstr::FrameDestroy, PACSym); in authenticateLR()
206 if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) { in authenticateLR()
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/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp28 const CSKYSubtarget *Subtarget; member in __anon1643caa60111::CSKYDAGToDAGISel
36 Subtarget = &MF.getSubtarget<CSKYSubtarget>(); in runOnMachineFunction()
92 Register GP = Subtarget->getInstrInfo()->getGlobalBaseReg(*MF); in INITIALIZE_PASS()
102 ReplaceNode(N, CurDAG->getMachineNode(Subtarget->hasE2() ? CSKY::ADDI32 in INITIALIZE_PASS()
290 if (!Subtarget->hasFPUv2DoubleFloat()) in selectBITCAST_TO_LOHI()
315 Subtarget->has2E3() ? CSKY::CLRC32 : CSKY::CLRC16, Dl, Type1); in selectAddCarry()
317 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
321 Subtarget->has2E3() ? CSKY::SETC32 : CSKY::SETC16, Dl, Type1); in selectAddCarry()
323 Subtarget->has2E3() ? CSKY::ADDC32 : CSKY::ADDC16, Dl, {Type0, Type1}, in selectAddCarry()
326 NewNode = CurDAG->getMachineNode(Subtarget->has2E3() ? CSKY::ADDC32 in selectAddCarry()
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H A DCSKY.td24 def HasFPUv2_SF : Predicate<"Subtarget->hasFPUv2SingleFloat()">,
31 def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">,
37 def HasFdivdu : Predicate<"Subtarget->hasFdivdu()">,
44 def HasFPUv3_HI : Predicate<"Subtarget->hasFPUv3HalfWord()">,
51 def HasFPUv3_HF : Predicate<"Subtarget->hasFPUv3HalfFloat()">,
58 def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">,
65 def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">,
71 def iHasFLOATE1 : Predicate<"Subtarget->hasFLOATE1()">,
77 def iHasFLOAT1E2 : Predicate<"Subtarget->hasFLOAT1E2()">,
83 def iHasFLOAT1E3 : Predicate<"Subtarget->hasFLOAT1E3()">,
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/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp79 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getRegAllocationHints() local
80 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); in getRegAllocationHints()
192 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
193 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_SaveList in getCalleeSavedRegs()
199 const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>(); in getCalleeSavedRegs() local
203 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList in getCalleeSavedRegs()
215 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
216 return Subtarget.hasVector() ? CSR_SystemZ_XPLINK64_Vector_RegMask in getCallPreservedMask()
223 const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>(); in getCallPreservedMask() local
227 return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask in getCallPreservedMask()
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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArch.td24 : Predicate<"Subtarget->is64Bit()">,
28 : Predicate<"!Subtarget->is64Bit()">,
39 def HasBasicF : Predicate<"Subtarget->hasBasicF()">;
46 def HasBasicD : Predicate<"Subtarget->hasBasicD()">;
52 def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">;
59 def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">;
65 def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">;
71 def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">;
78 : Predicate<"Subtarget->hasLaGlobalWithPcrel()">,
87 : Predicate<"Subtarget->hasLaGlobalWithAbs()">,
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