| /src/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenInstAlias.cpp | 236 for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) { in CodeGenInstAlias() local
237 Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef(); in CodeGenInstAlias()
243 MIOI->getArgName(SubOp)->getAsUnquotedString(), in CodeGenInstAlias()
245 ResultInstOperandIndex.push_back(std::pair(i, SubOp)); in CodeGenInstAlias()
256 for (unsigned SubOp = 0; SubOp != NumSubOps; ++SubOp) { in CodeGenInstAlias() local
259 Record *SubRec = cast<DefInit>(MIOI->getArg(SubOp))->getDef(); in CodeGenInstAlias()
263 ResultInstOperandIndex.push_back(std::pair(i, SubOp)); in CodeGenInstAlias()
270 (SubOp == 0 ? InstOpRec->getName() : SubRec->getName())); in CodeGenInstAlias()
|
| H A D | CodeGenInstruction.cpp | 222 StringRef Name, std::pair<unsigned, unsigned> &SubOp) const { in hasSubOperandAlias()
226 SubOp = SubOpIter->second; in hasSubOperandAlias()
254 if (std::pair<unsigned, unsigned> SubOp; hasSubOperandAlias(OpName, SubOp)) { in ParseOperandName() local
263 return SubOp; in ParseOperandName()
|
| H A D | CodeGenInstruction.h | 186 std::pair<unsigned, unsigned> &SubOp) const;
|
| /src/sys/contrib/dev/acpica/compiler/ |
| H A D | aslerror.c | 1515 ACPI_PARSE_OBJECT *SubOp, in AslDualParseOpError() argument
1529 if (SubOp) in AslDualParseOpError()
1531 AslInitEnode (&SubEnode, Level, SubMsgId, SubOp->Asl.LineNumber, in AslDualParseOpError()
1532 SubOp->Asl.LogicalLineNumber, SubOp->Asl.LogicalByteOffset, in AslDualParseOpError()
1533 SubOp->Asl.Column, SubOp->Asl.Filename, SubMsg, in AslDualParseOpError()
|
| /src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeEmitterGen.cpp | 123 std::pair<unsigned, unsigned> SubOp; in addCodeToMergeInOperand() local
124 if (CGI.Operands.hasSubOperandAlias(VarName, SubOp)) { in addCodeToMergeInOperand()
125 OpIdx = CGI.Operands[SubOp.first].MIOperandNo + SubOp.second; in addCodeToMergeInOperand()
|
| /src/contrib/llvm-project/llvm/lib/TableGen/ |
| H A D | SetTheory.cpp | 46 struct SubOp : public SetTheory::Operator { struct
258 addOperator("sub", std::make_unique<SubOp>()); in SetTheory()
|
| /src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 2033 Instruction *AddOp = nullptr, *SubOp = nullptr; in foldAddSubSelect() local
2039 SubOp = TI; in foldAddSubSelect()
2045 SubOp = FI; in foldAddSubSelect()
2050 if (SubOp->getOperand(0) == AddOp->getOperand(0)) { in foldAddSubSelect()
2052 } else if (SubOp->getOperand(0) == AddOp->getOperand(1)) { in foldAddSubSelect()
2061 NegVal = Builder.CreateFNeg(SubOp->getOperand(1)); in foldAddSubSelect()
2064 Flags &= SubOp->getFastMathFlags(); in foldAddSubSelect()
2068 NegVal = Builder.CreateNeg(SubOp->getOperand(1)); in foldAddSubSelect()
2080 BinaryOperator::CreateFAdd(SubOp->getOperand(0), NewSel); in foldAddSubSelect()
2083 Flags &= SubOp->getFastMathFlags(); in foldAddSubSelect()
[all …]
|
| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 1113 unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32; in SelectDS1Addr1Offset() local
1115 SubOp = AMDGPU::V_SUB_U32_e64; in SelectDS1Addr1Offset()
1121 CurDAG->getMachineNode(SubOp, DL, MVT::i32, Opnds); in SelectDS1Addr1Offset()
1298 unsigned SubOp = AMDGPU::V_SUB_CO_U32_e32; in SelectDSReadWrite2() local
1300 SubOp = AMDGPU::V_SUB_U32_e64; in SelectDSReadWrite2()
1306 SubOp, DL, MVT::getIntegerVT(Size * 8), Opnds); in SelectDSReadWrite2()
|
| H A D | SIInstrInfo.cpp | 7637 unsigned SubOp = ST.hasAddNoCarry() ? in lowerScalarAbs() local
7640 BuildMI(MBB, MII, DL, get(SubOp), TmpReg) in lowerScalarAbs()
|
| /src/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 4260 unsigned SubOp; in expandDivRem() local
4265 SubOp = Mips::DSUB; in expandDivRem()
4269 SubOp = Mips::SUB; in expandDivRem()
4305 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
|
| /src/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 2263 SDValue SubOp = Node->getOperand(i); in LowerCONCAT_VECTORS() local
2264 EVT VVT = SubOp.getNode()->getValueType(0); in LowerCONCAT_VECTORS()
2268 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
|
| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 3277 SDValue SubOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
3280 if (SimplifyDemandedVectorElts(SubOp, SubElts, SubUndef, SubZero, TLO, in SimplifyDemandedVectorElts()
3292 SDValue SubOp = Op.getOperand(i); in SimplifyDemandedVectorElts() local
3295 SubOp, SubElts, TLO.DAG, Depth + 1); in SimplifyDemandedVectorElts()
3296 DemandedSubOps.push_back(NewSubOp ? NewSubOp : SubOp); in SimplifyDemandedVectorElts()
|
| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 56176 for (SDValue SubOp : SubOps) in combineConcatVectorOps() local
56177 Subs.push_back(SubOp.getOperand(I)); in combineConcatVectorOps()
56886 if (all_of(SubVectorOps, [](SDValue SubOp) { in combineINSERT_SUBVECTOR() argument
56887 return isTargetShuffle(SubOp.getOpcode()); in combineINSERT_SUBVECTOR()
|