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Searched refs:Strided (Results 1 – 7 of 7) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h210 uint16_t Strided : 1; member
230 uint16_t Strided : 1; member
248 uint16_t Strided : 1; member
257 uint16_t Strided : 1; member
H A DRISCVInstrInfoVPseudos.td581 bits<1> Strided = Str;
596 let Fields = ["Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
597 let PrimaryKey = ["Masked", "Strided", "FF", "Log2SEW", "LMUL"];
603 bits<1> Strided = Str;
612 let Fields = ["Masked", "Strided", "Log2SEW", "LMUL", "Pseudo"];
613 let PrimaryKey = ["Masked", "Strided", "Log2SEW", "LMUL"];
650 bits<1> Strided = Str;
660 let Fields = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL", "Pseudo"];
661 let PrimaryKey = ["NF", "Masked", "Strided", "FF", "Log2SEW", "LMUL"];
686 bits<1> Strided = Str;
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H A DRISCVScheduleV.td292 // 7.4.1. Vector Unit-Strided Mask
295 // 7.5. Vector Strided Instructions
548 // 7.4.1. Vector Unit-Strided Mask
550 // 7.5. Vector Strided Instructions
H A DRISCVInstrInfoV.td196 // Vector Strided Loads and Stores
259 // Strided Segment Loads and Stores
1053 // Vector Strided Instructions
1722 // Vector Strided Instructions
1764 // Vector Strided Segment Instructions
H A DRISCVSchedSiFive7.td474 // Strided loads and stores operate at one element per cycle and should be
579 // segment loads and stores. Strided segment loads and stores operate at up to
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td1713 // Strided loads/stores for fixed vectors.
/src/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td709 // 7.5. Vector Strided Instructions