Searched refs:Sn (Results 1 – 9 of 9) sorted by relevance
| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 432 let TwoOperandAliasConstraint = "$Sn = $Sd" in 434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), 435 IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", 436 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>, 443 let TwoOperandAliasConstraint = "$Sn = $Sd" in 445 (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm), 446 IIC_fpALU16, "vadd", ".f16\t$Sd, $Sn, $Sm", 447 [(set (f16 HPR:$Sd), (fadd (f16 HPR:$Sn), (f16 HPR:$Sm)))]>, 457 let TwoOperandAliasConstraint = "$Sn = $Sd" in 459 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), [all …]
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| H A D | ARMInstrFormats.td | 1973 bits<5> Sn; 1979 let Inst{19-16} = Sn{4-1}; 1980 let Inst{7} = Sn{0}; 2000 bits<5> Sn; 2008 let Inst{19-16} = Sn{4-1}; 2009 let Inst{7} = Sn{0}; 2031 bits<5> Sn; 2037 let Inst{19-16} = Sn{4-1}; 2038 let Inst{7} = Sn{0}; 2108 bits<5> Sn; [all …]
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| /src/sys/contrib/ncsw/Peripherals/QM/ |
| H A D | fsl_qman.h | 597 volatile uint32_t Sn:6; member
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| /src/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 954 SDValue Sn, Sm; in buildHvxVectorReg() local 960 Sn = DAG.getConstant(Rn, dl, MVT::i32); in buildHvxVectorReg() 961 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg() 977 Sn = DAG.getConstant(Rn+HwLen/2, dl, MVT::i32); in buildHvxVectorReg() 979 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg()
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| /src/contrib/llvm-project/lld/MachO/ |
| H A D | Options.td | 1118 def Sn : Flag<["-"], "Sn">,
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 7046 def : Pat<(v4i32 (vector_insert v4i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))), 7047 (INSvi32lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0)>; 7048 def : Pat<(v2i32 (vector_insert v2i32:$src, (i32 (bitconvert (f32 FPR32:$Sn))), (i64 imm:$Immd))), 7051 imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$Sn, ssub), 0), 7053 def : Pat<(v2i64 (vector_insert v2i64:$src, (i64 (bitconvert (f64 FPR64:$Sn))), (i64 imm:$Immd))), 7054 (INSvi64lane V128:$src, imm:$Immd, (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$Sn, dsub), 0)>;
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| H A D | SVEInstrFormats.td | 1372 def : InstAlias<"mov $Zd, $Sn", 1373 (!cast<Instruction>(NAME # _S) ZPR32:$Zd, FPR32asZPR:$Sn, 0), 2>;
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| /src/contrib/netbsd-tests/usr.bin/netpgpverify/ |
| H A D | t_netpgpverify.sh | 4736 69B8yeCYt2bk6YfPsD09Pno6hfblMiwWIDHcbaeXIcMvv4xX/Sn++a//8St1AdAh 4836 713U/PVvfx+/fd7HucZve7827GYfMwlNqumpyxmmKvJZ4q2GtVMjBc2U9+9Sn/xZ
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| /src/contrib/sendmail/ |
| H A D | PGPKEYS | 3893 Sn/xUlHB9VGWBAXlq6qJcx2jqWGrmRfz8gMBAwfLTUyNNeixt3TReTtos/HaZK3X
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