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Searched refs:SingleIssue (Results 1 – 9 of 9) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM55.td69 // All instructions we cannot dual issue are "SingleIssue=1" (MVE/FP and T2
73 // one). These use normal resources and latencies, but set SingleIssue = 0.
76 // don't use a resource, and set SingleIssue = 0.
133 // SingleIssue = 0. The others are SingleIssue = 1.
134 let SingleIssue = 0, Latency = 1 in {
143 let SingleIssue = 1, Latency = 1 in {
176 // issues (SingleIssue = 0)
177 let SingleIssue = 0, Latency = 2 in {
181 let SingleIssue = 1, Latency = 2 in {
220 let Latency = 1, SingleIssue = 0 in {
[all …]
H A DARMScheduleM7.td90 let SingleIssue = 1;
165 let SingleIssue = 1;
191 let SingleIssue = 1;
285 let SingleIssue = 1;
295 let SingleIssue = 1;
299 let SingleIssue = 1;
435 def M7VMRS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
436 def M7VMSR : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
H A DARMSubtarget.h78 SingleIssue, enumerator
129 ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
H A DARMScheduleM85.td173 def M85SingleIssue : SchedWriteRes<[]> { let SingleIssue = 1; }
207 let SingleIssue = 1;
308 def M85TableLoad : SchedWriteRes<[M85UnitLoad]> { let SingleIssue = 1; }
601 let SingleIssue = 1 in {
H A DARMScheduleR52.td723 let SingleIssue = 1;
729 let SingleIssue = 1;
735 let SingleIssue = 1;
H A DARMBaseInstrInfo.cpp3848 case ARMSubtarget::SingleIssue: in getNumMicroOps()
/src/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td268 // SingleIssue is an alias for Begin/End Group.
269 bit SingleIssue = false;
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td96 def CortexA55WriteVLD1SI : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; let SingleIssue = 1;…
H A DAArch64SchedA510.td128 def CortexA510WriteVLD1SI : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; let SingleIssue = …