| /src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSimplifyDemanded.cpp | 89 bool InstCombinerImpl::SimplifyDemandedBits(Instruction *I, unsigned OpNo, in SimplifyDemandedBits() function in InstCombinerImpl 195 SimplifyDemandedBits(I, 0, DemandedFromOps, LHSKnown, Depth + 1, Q) || in SimplifyDemandedUseBits() 197 SimplifyDemandedBits(I, 1, DemandedFromOps, RHSKnown, Depth + 1, Q)) { in SimplifyDemandedUseBits() 210 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1, Q) || in SimplifyDemandedUseBits() 211 SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.Zero, LHSKnown, in SimplifyDemandedUseBits() 238 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1, Q) || in SimplifyDemandedUseBits() 239 SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.One, LHSKnown, in SimplifyDemandedUseBits() 278 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1, Q) || in SimplifyDemandedUseBits() 279 SimplifyDemandedBits(I, 0, DemandedMask, LHSKnown, Depth + 1, Q)) in SimplifyDemandedUseBits() 370 if (SimplifyDemandedBits(I, 2, DemandedMask, RHSKnown, Depth + 1, Q) || in SimplifyDemandedUseBits() [all …]
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| H A D | InstCombineInternal.h | 553 using InstCombiner::SimplifyDemandedBits; 554 bool SimplifyDemandedBits(Instruction *I, unsigned Op,
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| H A D | InstCombineCompares.cpp | 6455 if (SimplifyDemandedBits(&I, 0, getDemandedBitsLHSMask(I, BitWidth), in foldICmpUsingKnownBits() 6459 if (SimplifyDemandedBits(&I, 1, APInt::getAllOnes(BitWidth), Op1Known, in foldICmpUsingKnownBits()
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| H A D | InstCombineCalls.cpp | 2110 if (SimplifyDemandedBits(II, 2, Op2Demanded, Op2Known)) in visitCallInst()
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| /src/contrib/llvm-project/llvm/include/llvm/Transforms/InstCombine/ |
| H A D | InstCombiner.h | 505 virtual bool SimplifyDemandedBits(Instruction *I, unsigned OpNo, 509 bool SimplifyDemandedBits(Instruction *I, unsigned OpNo, in SimplifyDemandedBits() function 511 return SimplifyDemandedBits(I, OpNo, DemandedMask, Known, in SimplifyDemandedBits()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 620 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, in SimplifyDemandedBits() function in TargetLowering 627 bool Simplified = SimplifyDemandedBits(Op, DemandedBits, Known, TLO); in SimplifyDemandedBits() 635 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, in SimplifyDemandedBits() function in TargetLowering 644 SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO); in SimplifyDemandedBits() 652 bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, in SimplifyDemandedBits() function in TargetLowering 665 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth, in SimplifyDemandedBits() 1101 bool TargetLowering::SimplifyDemandedBits( in SimplifyDemandedBits() function in TargetLowering 1174 if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1)) in SimplifyDemandedBits() 1192 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) in SimplifyDemandedBits() 1238 if (SimplifyDemandedBits(Scl, DemandedSclBits, KnownScl, TLO, Depth + 1)) in SimplifyDemandedBits() [all …]
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| H A D | DAGCombiner.cpp | 336 bool SimplifyDemandedBits(SDValue Op) { in SimplifyDemandedBits() function in __anon455bbfa50111::DAGCombiner 339 return SimplifyDemandedBits(Op, DemandedBits); in SimplifyDemandedBits() 342 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) { in SimplifyDemandedBits() function in __anon455bbfa50111::DAGCombiner 347 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, false); in SimplifyDemandedBits() 363 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 1378 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, in SimplifyDemandedBits() function in DAGCombiner 1383 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0, in SimplifyDemandedBits() 2813 if (SimplifyDemandedBits(SDValue(N, 0))) in visitADDLike() 4565 if (SimplifyDemandedBits(SDValue(N, 0))) in visitMUL() 5185 if (SimplifyDemandedBits(SDValue(N, 0))) in visitMULHU() [all …]
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4004 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 4011 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 4018 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits, 4023 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
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| /src/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1513 TLI.SimplifyDemandedBits(OutVal, DemandedMask, Known, TLO)) in PerformDAGCombine() 1529 TLI.SimplifyDemandedBits(Time, DemandedMask, Known, TLO)) in PerformDAGCombine()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 189 if (IC.SimplifyDemandedBits(&II, 0, APInt::getLowBitsSet(32, 16), in instCombineIntrinsic() 226 if (IC.SimplifyDemandedBits(&II, CarryOp, APInt::getOneBitSet(32, 29), in instCombineIntrinsic()
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| H A D | ARMISelLowering.cpp | 15217 if (TLI.SimplifyDemandedBits(Op0, DemandedMask, DCI)) in PerformVMOVhrCombine() 15421 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI)) in PerformPREDICATE_CASTCombine() 17662 if (SimplifyDemandedBits(N->getOperand(3), DemandedMask, DCI)) in PerformIntrinsicCombine() 17679 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformIntrinsicCombine() 19001 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine() 19008 if (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI)) in PerformDAGCombine() 19019 if ((SimplifyDemandedBits(N->getOperand(0), DemandedMask, DCI)) || in PerformDAGCombine() 19020 (SimplifyDemandedBits(N->getOperand(1), DemandedMask, DCI))) in PerformDAGCombine() 19029 if ((SimplifyDemandedBits(N->getOperand(0), LowMask, DCI)) || in PerformDAGCombine() 19030 (SimplifyDemandedBits(N->getOperand(1), HighMask, DCI))) in PerformDAGCombine() [all …]
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 42665 if (SimplifyDemandedBits(Src, TruncMask, DemandedElts, KnownOp, TLO, Depth + 1)) in SimplifyDemandedBitsForTargetNode() 42688 if (SimplifyDemandedBits(LHS, DemandedMaskLHS, OriginalDemandedElts, in SimplifyDemandedBitsForTargetNode() 42691 if (SimplifyDemandedBits(RHS, DemandedMaskRHS, OriginalDemandedElts, in SimplifyDemandedBitsForTargetNode() 42722 if (SimplifyDemandedBits(Op1, OriginalDemandedBits, OriginalDemandedElts, in SimplifyDemandedBitsForTargetNode() 42726 if (SimplifyDemandedBits(Op0, ~Known.Zero & OriginalDemandedBits, in SimplifyDemandedBitsForTargetNode() 42775 if (SimplifyDemandedBits(Op0, DemandedMask, OriginalDemandedElts, Known, in SimplifyDemandedBitsForTargetNode() 42793 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, in SimplifyDemandedBitsForTargetNode() 42833 if (SimplifyDemandedBits(Op0, DemandedMask, OriginalDemandedElts, Known, in SimplifyDemandedBitsForTargetNode() 42898 if (SimplifyDemandedBits(Vec, DemandedVecBits, DemandedVecElts, in SimplifyDemandedBitsForTargetNode() 42927 if (SimplifyDemandedBits(Vec, OriginalDemandedBits, DemandedVecElts, in SimplifyDemandedBitsForTargetNode() [all …]
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.td | 1884 // occurs because SimplifyDemandedBits prefers srl over sra. 1889 // SimplifyDemandedBits.
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| H A D | RISCVISelLowering.cpp | 16669 if (!SimplifyDemandedBits(Op, Mask, DCI)) in PerformDAGCombine()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3745 if (TLI.SimplifyDemandedBits(LHS, Demanded, DCI)) in simplifyMul24() 3747 if (TLI.SimplifyDemandedBits(RHS, Demanded, DCI)) in simplifyMul24() 5234 TLI.SimplifyDemandedBits(BitsFrom, Demanded, Known, TLO)) { in PerformDAGCombine()
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| H A D | SIISelLowering.cpp | 14637 if (TLI.SimplifyDemandedBits(Src, DemandedBits, DCI)) { in performCvtF32UByteNCombine()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 22401 if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI)) in performVectorShiftCombine() 22550 if (TLI.SimplifyDemandedBits(Addr, DemandedMask, Known, TLO)) { in performTBISimplification() 25295 if (DAG.getTargetLoweringInfo().SimplifyDemandedBits( in PerformDAGCombine()
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