| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MacroFusion.cpp | 23 const MachineInstr &SecondMI, bool CmpOnly) { in isArithmeticBccPair() argument
24 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
72 const MachineInstr &SecondMI) { in isArithmeticCbzPair() argument
73 if (SecondMI.getOpcode() != AArch64::CBZW && in isArithmeticCbzPair()
74 SecondMI.getOpcode() != AArch64::CBZX && in isArithmeticCbzPair()
75 SecondMI.getOpcode() != AArch64::CBNZW && in isArithmeticCbzPair()
76 SecondMI.getOpcode() != AArch64::CBNZX) in isArithmeticCbzPair()
122 const MachineInstr &SecondMI) { in isAESPair() argument
124 switch (SecondMI.getOpcode()) { in isAESPair()
140 const MachineInstr &SecondMI) { in isCryptoEORPair() argument
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| /src/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMacroFusion.cpp | 70 const MachineInstr &SecondMI, in matchingRegOps() argument
73 const MachineOperand &Op2 = SecondMI.getOperand(SecondMIOpIndex); in matchingRegOps()
97 const MachineInstr &SecondMI) { in checkOpConstraints() argument
105 const MachineOperand &RA = SecondMI.getOperand(1); in checkOpConstraints()
114 const MachineOperand &RT = SecondMI.getOperand(0); in checkOpConstraints()
122 if (!matchingRegOps(SecondMI, 0, SecondMI, 2) || in checkOpConstraints()
137 const MachineOperand &D = SecondMI.getOperand(1); in checkOpConstraints()
143 if (SecondMI.getOpcode() == PPC::LD) in checkOpConstraints()
171 const MachineOperand &BT = SecondMI.getOperand(0); in checkOpConstraints()
174 if (SecondMI.getOpcode() == PPC::CMPDI && in checkOpConstraints()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNCreateVOPD.cpp | 48 : FirstMI(First), SecondMI(Second) {} in VOPDCombineInfo()
51 MachineInstr *SecondMI; member in __anon0af83bcd0111::GCNCreateVOPD::VOPDCombineInfo
71 auto *SecondMI = CI.SecondMI; in doReplace() local
73 unsigned Opc2 = SecondMI->getOpcode(); in doReplace()
84 .setMIFlags(FirstMI->getFlags() | SecondMI->getFlags()); in doReplace()
87 MachineInstr *MI[] = {FirstMI, SecondMI}; in doReplace()
89 AMDGPU::getVOPDInstInfo(FirstMI->getDesc(), SecondMI->getDesc()); in doReplace()
109 << *CI.FirstMI << "\tY: " << *CI.SecondMI << "\n"); in doReplace()
140 auto *SecondMI = &*MII; in runOnMachineFunction() local
142 unsigned Opc2 = SecondMI->getOpcode(); in runOnMachineFunction()
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| H A D | GCNVOPDUtils.cpp | 39 const MachineInstr &SecondMI) { in checkVOPDRegConstraints() argument
59 if (&*MII == &SecondMI) in checkVOPDRegConstraints()
65 for (const auto &Use : SecondMI.uses()) in checkVOPDRegConstraints()
70 const MachineInstr &MI = (OpcodeIdx == VOPD::X) ? FirstMI : SecondMI; in checkVOPDRegConstraints()
78 AMDGPU::getVOPDInstInfo(FirstMI.getDesc(), SecondMI.getDesc()); in checkVOPDRegConstraints()
81 const MachineInstr &MI = (CompIdx == VOPD::X) ? FirstMI : SecondMI; in checkVOPDRegConstraints()
110 SecondMI.getOpcode() == AMDGPU::V_MOV_B32_e32; in checkVOPDRegConstraints()
116 << "\n\tY: " << SecondMI << "\n"); in checkVOPDRegConstraints()
126 const MachineInstr &SecondMI) { in shouldScheduleVOPDAdjacent() argument
128 unsigned Opc2 = SecondMI.getOpcode(); in shouldScheduleVOPDAdjacent()
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| H A D | AMDGPUMacroFusion.cpp | 29 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
32 switch (SecondMI.getOpcode()) { in shouldScheduleAdjacent()
46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent()
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| H A D | GCNVOPDUtils.h | 26 const MachineInstr &SecondMI);
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMMacroFusion.cpp | 23 const MachineInstr &SecondMI) { in isAESPair() argument
25 switch(SecondMI.getOpcode()) { in isAESPair()
39 const MachineInstr &SecondMI) { in isLiteralsPair() argument
42 SecondMI.getOpcode() == ARM::MOVTi16) in isLiteralsPair()
54 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
57 if (ST.hasFuseAES() && isAESPair(FirstMI, SecondMI)) in shouldScheduleAdjacent()
59 if (ST.hasFuseLiterals() && isLiteralsPair(FirstMI, SecondMI)) in shouldScheduleAdjacent()
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| /src/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetMacroFusion.td | 22 // * const MachineInstr &SecondMI
49 // `firstOpIdx` should be the same as the operand of `SecondMI` at position
58 // The operand of `SecondMI` at position `firstOpIdx` should be the same as the
89 // const MachineInstr &SecondMI) {
90 // auto &MRI = SecondMI.getMF()->getRegInfo();
108 // const MachineInstr &SecondMI) {
109 // auto &MRI = SecondMI.getMF()->getRegInfo();
111 // /* Predicate for `SecondMI` */
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86MacroFusion.cpp | 38 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
45 const X86::SecondMacroFusionInstKind BranchKind = classifySecond(SecondMI); in shouldScheduleAdjacent()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MacroFusion.cpp | 154 const MachineInstr &SecondMI);
162 const MachineInstr &SecondMI) { in shouldScheduleAdjacent() argument
164 return Predicate(TII, STI, FirstMI, SecondMI); in shouldScheduleAdjacent()
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| /src/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MacroFusion.h | 35 const MachineInstr &SecondMI);
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandPseudoInsts.cpp | 535 MachineInstr *SecondMI = in expandAuipcInstPair() local
541 SecondMI->addMemOperand(*MF, *MI.memoperands_begin()); in expandAuipcInstPair()
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| /src/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandPseudoInsts.cpp | 150 MachineInstr *SecondMI = in expandPcalau12iInstPair() local
156 SecondMI->addMemOperand(*MF, *MI.memoperands_begin()); in expandPcalau12iInstPair()
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