| /src/sys/contrib/device-tree/src/arm64/marvell/ |
| H A D | cn9131-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
| H A D | cn9132-db-B.dts | 15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
| H A D | cn9132-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
| H A D | cn9130-db.dts | 14 /* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash.
15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
|
| H A D | cn9130-db-B.dts | 15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
| H A D | cn9131-db-B.dts | 15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
16 * simultaneously. When NAND controller is enabled, SPI1 should be disabled.
|
| H A D | armada-8040-clearfog-gt-8k.dts | 433 * [13] CP1 SPI1 MISO (TDM and SPI ROM shared)
434 * [14] CP1 SPI1 CS0n (64Mb SPI ROM)
435 * [15] CP1 SPI1 MOSI (TDM and SPI ROM shared)
436 * [16] CP1 SPI1 CLK (TDM and SPI ROM shared)
|
| /src/sys/contrib/device-tree/Bindings/spi/ |
| H A D | brcm,bcm2835-aux-spi.txt | 1 Broadcom BCM2835 auxiliary SPI1/2 controller
5 auxiliary block. This binding applies to the SPI1/2 controller.
|
| H A D | fsl-spi.txt | 5 0: QE subblock SPI1
|
| /src/sys/contrib/device-tree/src/arm/nvidia/ |
| H A D | tegra30-apalis-eval.dts | 117 /* SPI1: Apalis SPI1 */
|
| H A D | tegra124-apalis-v1.2-eval.dts | 114 /* SPI1: Apalis SPI1 */
|
| H A D | tegra124-apalis-eval.dts | 112 /* SPI1: Apalis SPI1 */
|
| H A D | tegra30-apalis-v1.1-eval.dts | 118 /* SPI1: Apalis SPI1 */
|
| /src/sys/contrib/device-tree/Bindings/clock/ |
| H A D | brcm,bcm2835-aux-clock.txt | 6 The auxiliary peripherals (UART, SPI1, and SPI2) have a small register
|
| /src/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | rda,8810pl-intc.txt | 24 6: SPI1
|
| /src/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8-apalis-eval.dtsi | 57 /* Apalis SPI1 */
|
| H A D | imx8-apalis-ixora-v1.1.dtsi | 132 /* Apalis SPI1 */
|
| /src/sys/contrib/device-tree/Bindings/net/nfc/ |
| H A D | trf7970a.txt | 22 Example (for ARM-based BeagleBone with TRF7970A on SPI1):
|
| /src/sys/contrib/device-tree/src/arm/intel/socfpga/ |
| H A D | socfpga_cyclone5_chameleon96.dts | 102 label = "HS-SPI1";
|
| /src/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3399-rock960.dts | 138 /* On High speed expansion (HS-SPI1) */
|
| /src/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | stm32mp1-clks.h | 50 #define SPI1 37 macro
|
| /src/sys/contrib/device-tree/src/mips/mobileye/ |
| H A D | eyeq6h-pins.dtsi | 53 pinctrl-single,pins = <0x0a4 1>; // SPI1 pin group
|
| /src/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6ull-dhcor-som.dtsi | 58 * DHCOM SPI1 interface or accessing the SPI bootflash. Both using
59 * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses
|
| H A D | imx6qdl-var-dart.dtsi | 222 /* SPI1 CS0 */
224 /* SPI1 CS1 */
|
| /src/sys/contrib/device-tree/src/arm/aspeed/ |
| H A D | aspeed-g6-pinctrl.dtsi | 666 function = "SPI1";
931 function = "SPI1";
932 groups = "SPI1";
|