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Searched refs:SLLW (Results 1 – 10 of 10) sorted by relevance

/src/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h151 R_TYPE_INST(SLLW);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
H A DEmulateInstructionRISCV.cpp465 {"SLLW", 0xFE00707F, 0x103B, DecodeRType<SLLW>},
948 bool operator()(SLLW inst) { in operator ()()
/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVGISel.td93 def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
H A DRISCVOptWInstrs.cpp162 case RISCV::SLLW: in hasAllNBitUsers()
H A DRISCVExpandPseudoInsts.cpp226 case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break; in expandCCOp()
H A DRISCVInstrInfo.td74 def riscv_sllw : SDNode<"RISCVISD::SLLW", SDT_RISCVIntBinOpW>;
770 def SLLW : ALUW_rr<0b0000000, 0b001, "sllw">,
1826 // PatFrag to allow ADDW/SUBW/MULW/SLLW to be selected from i64 add/sub/mul/shl
1872 def : PatGprGpr<shiftopw<riscv_sllw>, SLLW>;
2002 def : PatGprGpr<shiftopw<shl>, SLLW, i32, i64>;
H A DRISCVISelLowering.h70 SLLW, enumerator
H A DRISCVInstrInfo.cpp1315 case RISCV::SLLW: return RISCV::PseudoCCSLLW; break; in getPredicatedOpcode()
H A DRISCVISelDAGToDAG.cpp3134 case RISCV::SLLW: in hasAllNBitUsers()
H A DRISCVISelLowering.cpp12141 return RISCVISD::SLLW; in getRISCVWOpcode()
13815 if (N0.getOpcode() == RISCVISD::SLLW && in performXORCombine()
16726 case RISCVISD::SLLW: in PerformDAGCombine()
17865 case RISCVISD::SLLW: { in computeKnownBitsForTargetNode()
17978 case RISCVISD::SLLW: in ComputeNumSignBitsForTargetNode()
20395 NODE_NAME_CASE(SLLW) in getTargetNodeName()