Home
last modified time | relevance | path

Searched refs:SLLI (Results 1 – 23 of 23) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMacroFusion.td36 "Enable SLLI+SRLI to be fused to zero extension of halfword",
38 CheckOpcode<[SLLI]>,
53 "Enable SLLI+SRLI to be fused to zero extension of word",
55 CheckOpcode<[SLLI]>,
71 "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
73 CheckOpcode<[SLLI]>,
H A DRISCVISelDAGToDAG.cpp227 SDValue SLLI = SDValue( in selectImm() local
228 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, Lo, in selectImm()
231 return SDValue(CurDAG->getMachineNode(AddOpc, DL, VT, Lo, SLLI), 0); in selectImm()
670 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI; in tryShrinkShlLogicImm()
675 SDNode *SLLI = in tryShrinkShlLogicImm() local
678 ReplaceNode(Node, SLLI); in tryShrinkShlLogicImm()
1093 SDNode *SLLI = CurDAG->getMachineNode( in Select() local
1094 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0), in Select()
1096 ReplaceNode(Node, SLLI); in Select()
1122 SDNode *SLLI = CurDAG->getMachineNode( in Select() local
[all …]
H A DRISCVOptWInstrs.cpp218 case RISCV::SLLI: in hasAllNBitUsers()
586 case RISCV::SLLI: in isSignExtendedW()
621 case RISCV::SLLI: in getWOp()
696 case RISCV::SLLIW: Opc = RISCV::SLLI; break; in stripWSuffixes()
733 case RISCV::SLLI: in appendWSuffixes()
H A DRISCVInstrInfoM.td115 (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
H A DRISCVVectorPeephole.cpp94 if (Def->getOpcode() == RISCV::SLLI) { in convertToVLMAX()
H A DRISCVInstrInfo.td664 def SLLI : Shift_ri<0b00000, 0b001, "slli">;
1030 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1266 def : PatGprUimmLog2XLen<shl, SLLI>;
1288 (SRAI (XLenVT (SLLI $rs, (ImmSubFromXLen (XLenVT 1)))),
1293 (SLLI (i64 (SRLI $rs, LeadingOnesMask:$mask)), LeadingOnesMask:$mask)>;
1295 (SRLI (XLenVT (SLLI $rs, TrailingOnesMask:$mask)), TrailingOnesMask:$mask)>;
1812 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (i64 (SLLI GPR:$rs1, 32)), 32)>;
1817 (SRLI (i64 (SLLI GPR:$rs1, 32)), (ImmSubFrom32 uimm5:$shamt))>;
1852 (SLLI (i64 (SRLIW $rs, LeadingOnesWMask:$mask)), LeadingOnesWMask:$mask)>;
2020 (SRLI (i32 (SLLI $rs, (i64 (XLenSubTrailingOnes $mask)))),
[all …]
H A DRISCVRegisterInfo.cpp352 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVSPILL()
429 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVRELOAD()
862 case RISCV::SLLI: in getRegAllocationHints()
H A DRISCVInstrInfo.cpp1306 case RISCV::SLLI: return RISCV::PseudoCCSLLI; break; in getPredicatedOpcode()
2102 const MachineInstr *ShiftMI = canCombine(MBB, MO, RISCV::SLLI); in canCombineShiftIntoShXAdd()
3667 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in mulImm()
3691 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in mulImm()
3702 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in mulImm()
3713 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in mulImm()
3734 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in mulImm()
H A DRISCVExpandPseudoInsts.cpp218 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break; in expandCCOp()
H A DRISCVInstrInfoXTHead.td558 (SLLI (XLenVT (TH_ADDSL (XLenVT (TH_ADDSL GPR:$r, GPR:$r, 2)),
586 (TH_FF0 (i64 (SLLI (i64 (XORI i64:$rs1, -1)), 32)))>;
H A DRISCVAsmPrinter.cpp658 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8), in EmitHwasanMemaccessSymbols()
H A DRISCVFrameLowering.cpp739 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
H A DRISCVInstrInfoC.td983 def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
/src/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp25 case RISCV::SLLI: in getInstSeqCost()
150 unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI; in generateInstSeqImpl()
248 TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros); in generateInstSeq()
537 case RISCV::SLLI: in getOpndKind()
/src/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h142 R_SHAMT_TYPE_INST(SLLI);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
H A DRISCVCInstructions.h233 return SLLI{rd, rd, uint8_t(shamt)}; in DecodeC_SLLI()
H A DEmulateInstructionRISCV.cpp443 {"SLLI", 0xF800707F, 0x1013, DecodeRShamtType<SLLI>},
877 bool operator()(SLLI inst) { in operator ()()
/src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp371 .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) in selectSHXADD_UWOp()
647 MIB.buildInstr(RISCV::SLLI, {&RISCV::GPRRegClass}, {MI.getOperand(2)}) in select()
/src/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td167 def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa),
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td441 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
H A DMipsScheduleGeneric.td1562 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
/src/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3325 emitToStreamer(Out, MCInstBuilder(RISCV::SLLI) in emitPseudoExtend()
/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td553 // Check if (mul r, imm) can be optimized to (SLLI (ALSL r, r, i0), i1),