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Searched refs:SIMD (Results 1 – 25 of 56) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArch.td48 // Loongson SIMD eXtension (LSX)
51 "'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>;
54 // Loongson Advanced SIMD eXtension (LASX)
57 "'LASX' (Loongson Advanced SIMD Extension)",
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td556 // 4.2.28 Advanced SIMD, Integer, 2 cycle
567 // 4.2.29 Advanced SIMD, Integer, 4 cycle
568 // 4.2.30 Advanced SIMD, Integer with Accumulate
577 // 4.2.31 Advanced SIMD, Add and Shift with Narrow
584 // 4.2.32 Advanced SIMD, Vector Table Lookup
597 // 4.2.33 Advanced SIMD, Transpose
602 // 4.2.34 Advanced SIMD and VFP, Floating Point
612 // 4.2.35 Advanced SIMD and VFP, Multiply
622 // 4.2.36 Advanced SIMD and VFP, Convert
625 // 4.2.37 Advanced SIMD and VFP, Move
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedOryon.td99 // Port 12: FP/Neon/SIMD/Crypto.
104 // Port 13: FP/Neon/SIMD/Crypto.
109 // Port 14: FP/Neon/SIMD/Crypto.
112 // Port 15: FP/Neon/SIMD/Crypto.
361 // 5 (4+1) for VXU SIMD access/could also include FP
1410 // SIMD move instructions
1431 // SIMD arithmetic instructions
1463 // SIMD compare instructions
1475 // SIMD widening and narrowing arithmetic instructions
1490 // SIMD unary arithmetic instructions
[all …]
H A DAArch64SchedA510.td56 def CortexA510UnitVALU0 : ProcResource<1>; // SIMD/FP/SVE ALU0
57 def CortexA510UnitVALU1 : ProcResource<1>; // SIMD/FP/SVE ALU0
58 def CortexA510UnitVMAC : ProcResource<2>; // SIMD/FP/SVE MAC
59 …def CortexA510UnitVMC : ProcResource<1>; // SIMD/FP/SVE multicycle instrs (e.g Div, SQRT, c…
399 // 4.15. Advanced SIMD integer instructions
442 // SIMD max/min, reduce
773 // Conditional extract operations, SIMD&FP scalar and vector forms
796 // Copy, scalar SIMD&FP or imm
834 // Extract/insert operation, SIMD and FP scalar form
H A DAArch64SchedFalkorDetails.td584 // SIMD Floating-point Instructions
656 // SIMD Integer Instructions
779 // SIMD Load Instructions
907 // SIMD Miscellaneous Instructions
966 // SIMD Store Instructions
H A DAArch64SchedA55.td387 // 4.15. Advanced SIMD integer instructions
430 // SIMD max/min, reduce
H A DAArch64SchedThunderX3T110.td57 // Port 6: FP/Neon/SIMD/Crypto.
60 // Port 7: FP/Neon/SIMD/Crypto.
63 // Port 8: FP/Neon/SIMD/Crypto.
66 // Port 9: FP/Neon/SIMD/Crypto.
H A DAArch64SchedThunderX2T99.td40 // Port 0: ALU, FP/SIMD.
43 // Port 1: ALU, FP/SIMD, integer mul/div.
74 // Crypto FP/SIMD micro-ops only on port 1.
77 // FP/SIMD micro-ops on ports 0 and 1.
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP10InstrResources.td1460 // 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands
1466 // 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands
1479 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands
1505 // 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands
1518 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands
1545 // 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands
1552 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix…
H A DPPCScheduleP7.td44 // Implemented as two 2-way SIMD operations for double- and single-precision.
53 // Executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops
H A DPPCScheduleP10.td50 def P10_MM : ProcResource<2>; // Two 512-bit SIMD matrix multiply engine pipelines.
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsWebAssembly.td182 // SIMD intrinsics
271 // Relaxed SIMD intrinsics (experimental)
/src/contrib/llvm-project/clang/include/clang/Basic/
H A DBuiltinsWebAssembly.def68 // SIMD builtins
168 // Relaxed SIMD builtins
/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssembly.td75 "Enable 128-bit SIMD">;
H A DWebAssemblyInstrSIMD.td1 // WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
10 /// WebAssembly SIMD operand code-gen constructs.
14 // Instructions using the SIMD opcode prefix and requiring one of the SIMD
452 // Constructing SIMD values
1012 // WebAssembly SIMD shifts are nonstandard in that the shift amount is
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleAtom.td36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide
38 // SIMD/FP: SIMD ALU, FP Adder
H A DX86CallingConv.td261 // Boolean vectors of AVX-512 are returned in SIMD registers.
581 // Boolean vectors of AVX-512 are passed in SIMD registers.
863 // Boolean vectors of AVX-512 are passed in SIMD registers.
/src/contrib/llvm-project/llvm/lib/Support/BLAKE3/
H A DREADME.md268 query the CPU at runtime to detect SIMD support, and it will use the
273 For each of the x86 SIMD instruction sets, four versions are available:
/src/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DPPCTargetParser.def115 PPC_LNX_FEATURE("altivec","CPU has a SIMD/Vector Unit",PPCF_ALTIVEC,0x10000000,PPC_FAWORD_HWCAP)
195 PPC_AIX_FEATURE("altivec","CPU has a SIMD/Vector Unit",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,ICmpInst::…
/src/crypto/openssl/test/recipes/30-test_evp_data/
H A Devpmac_poly1305.txt167 # 4th power of the key spills to 131th bit in SIMD key setup
/src/sys/contrib/openzfs/config/
H A Dtoolchain-simd.m43 dnl # Checks if host toolchain supports SIMD instructions
/src/crypto/openssl/crypto/aes/asm/
H A Dbsaes-armv8.pl1496 // 8*8 bytes: storage for 8 callee-saved SIMD registers
1846 …[0], v11.d[1] // just in case AES_encrypt corrupts top half of callee-saved SIMD registers
1885 …[0], v11.d[1] // just in case AES_encrypt corrupts top half of callee-saved SIMD registers
/src/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLICM.cpp1285 auto *SIMD = MSSA->getMemoryAccess(SI); in canSinkOrHoistInst() local
1287 auto *Source = getClobberingMemoryAccess(*MSSA, BAA, Flags, SIMD); in canSinkOrHoistInst()
1311 if (!Flags.getIsSink() && !MSSA->dominates(SIMD, MU)) in canSinkOrHoistInst()
/src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td127 // On machines without SIMD support, i128 is not a legal type, so model the
/src/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def682 // 128-bit SIMD registers

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