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Searched refs:SET4 (Results 1 – 3 of 3) sorted by relevance

/src/sys/arm/freescale/imx/
H A Dimx_gpio.c75 #define SET4(_sc, _r, _m) \ macro
353 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); in gpio_pic_setup_intr()
386 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq)); in gpio_pic_setup_intr()
422 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); in gpio_pic_enable_intr()
555 SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin)); in imx51_gpio_pin_configure()
556 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); in imx51_gpio_pin_configure()
661 SET4(sc, IMX_GPIO_DR_REG, (1U << pin)); in imx51_gpio_pin_set()
H A Dimx_gpt.c54 #define SET4(_sc, _r, _m) \ macro
/src/sys/arm/allwinner/
H A Daw_usbphy.c183 #define SET4(res, o, m) WR4(res, o, RD4(res, o) | (m)) macro
222 SET4(sc->pmu[phyno], PMU_IRQ_ENABLE, PMU_ULPI_BYPASS | in awusbphy_configure()
464 SET4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG); in awusbphy_set_mode()