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Searched refs:RotateVT (Results 1 – 2 of 2) sorted by relevance

/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp4948 MVT &RotateVT, unsigned &RotateAmt) { in isLegalBitRotate() argument
4958 RotateVT = MVT::getVectorVT(MVT::getIntegerVT(EltSizeInBits * NumSubElts), in isLegalBitRotate()
4962 return Subtarget.getTargetLowering()->isTypeLegal(RotateVT); in isLegalBitRotate()
4975 MVT RotateVT; in lowerVECTOR_SHUFFLEAsRotate() local
4976 if (!isLegalBitRotate(SVN, DAG, Subtarget, RotateVT, RotateAmt)) in lowerVECTOR_SHUFFLEAsRotate()
4979 SDValue Op = DAG.getBitcast(RotateVT, SVN->getOperand(0)); in lowerVECTOR_SHUFFLEAsRotate()
4984 if (RotateVT.getScalarType() == MVT::i16 && RotateAmt == 8) in lowerVECTOR_SHUFFLEAsRotate()
4985 Rotate = DAG.getNode(ISD::BSWAP, DL, RotateVT, Op); in lowerVECTOR_SHUFFLEAsRotate()
4987 Rotate = DAG.getNode(ISD::ROTL, DL, RotateVT, Op, in lowerVECTOR_SHUFFLEAsRotate()
4988 DAG.getConstant(RotateAmt, DL, RotateVT)); in lowerVECTOR_SHUFFLEAsRotate()
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/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp11274 static int matchShuffleAsBitRotate(MVT &RotateVT, int EltSizeInBits, in matchShuffleAsBitRotate() argument
11289 RotateVT = MVT::getVectorVT(RotateSVT, NumElts / NumSubElts); in matchShuffleAsBitRotate()
11305 MVT RotateVT; in lowerShuffleAsBitRotate() local
11306 int RotateAmt = matchShuffleAsBitRotate(RotateVT, VT.getScalarSizeInBits(), in lowerShuffleAsBitRotate()
11319 unsigned SrlAmt = RotateVT.getScalarSizeInBits() - RotateAmt; in lowerShuffleAsBitRotate()
11320 V1 = DAG.getBitcast(RotateVT, V1); in lowerShuffleAsBitRotate()
11321 SDValue SHL = DAG.getNode(X86ISD::VSHLI, DL, RotateVT, V1, in lowerShuffleAsBitRotate()
11323 SDValue SRL = DAG.getNode(X86ISD::VSRLI, DL, RotateVT, V1, in lowerShuffleAsBitRotate()
11325 SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL); in lowerShuffleAsBitRotate()
11330 DAG.getNode(X86ISD::VROTLI, DL, RotateVT, DAG.getBitcast(RotateVT, V1), in lowerShuffleAsBitRotate()