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Searched refs:RegisterClassHierarchy (Results 1 – 1 of 1) sorted by relevance

/src/contrib/llvm-project/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp66 const CodeGenRegBank &RegisterClassHierarchy) const { in getExplicitlySpecifiedRegisterClasses()
69 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef)); in getExplicitlySpecifiedRegisterClasses()
175 const CodeGenRegBank &RegisterClassHierarchy, in visitRegisterBankClasses() argument
187 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()
193 visitRegisterBankClasses(RegisterClassHierarchy, &PossibleSubclass, in visitRegisterBankClasses()
203 for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) { in visitRegisterBankClasses()
204 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()
218 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation() local
225 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()
253 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
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