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Searched refs:RegisterClass (Results 1 – 25 of 99) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.td152 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
165 def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
170 def R600_Addr_Y : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Y)>;
171 def R600_Addr_Z : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_Z)>;
172 def R600_Addr_W : RegisterClass <"AMDGPU", [i32], 32, (add Addr0_W)>;
174 def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32,
177 def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32,
180 def R600_KC0_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
183 def R600_KC0_Z : RegisterClass <"AMDGPU", [f32, i32], 32,
186 def R600_KC0_W : RegisterClass <"AMDGPU", [f32, i32], 32,
[all …]
H A DMIMGInstructions.td261 list<RegisterClass> addr_types=!listsplat(VGPR_32, num_addrs)>
273 class PartialNSAHelper<int num_addrs, int max_addr, RegisterClass LastAddrRC>
276 list<RegisterClass> addr_types =
359 list<RegisterClass> addr_types=[],
360 RegisterClass LastAddrRC = VGPR_32>
379 list<RegisterClass> addr_types=[]>
401 RegisterClass Addr3RC>
421 RegisterClass dst_rc,
422 RegisterClass addr_rc,
434 RegisterClass dst_rc,
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H A DDSInstructions.td99 class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
110 class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
121 multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
129 multiclass DS_1A1D_NORET_mc_gfx9<string opName, RegisterClass rc = VGPR_32> {
135 class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32,
146 multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
154 class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32,
166 multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
174 class DS_0A1D_RET_GDS<string opName, RegisterClass rc = VGPR_32, RegisterClass src = rc,
189 class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
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/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterInfo.td28 def TYPE : RegisterClass<"SPIRV", [i32], 32, (add TYPE0)>;
42 def ID : RegisterClass<"SPIRV", [i32], 32, (add ID0)>;
43 def ID64 : RegisterClass<"SPIRV", [i64], 32, (add ID640)>;
44 def fID : RegisterClass<"SPIRV", [f32], 32, (add fID0)>;
45 def fID64 : RegisterClass<"SPIRV", [f64], 32, (add fID640)>;
46 def pID32 : RegisterClass<"SPIRV", [p32], 32, (add pID320)>;
47 def pID64 : RegisterClass<"SPIRV", [p64], 32, (add pID640)>;
48 def vID : RegisterClass<"SPIRV", [v2i32], 32, (add vID0)>;
49 def vfID : RegisterClass<"SPIRV", [v2f32], 32, (add vfID0)>;
50 def vpID32 : RegisterClass<"SPIRV", [v2p32], 32, (add vpID320)>;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td284 RegisterClass<"Mips", regTypes, 32, (add
300 def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add
304 def GPR32NONZERO : RegisterClass<"Mips", [i32], 32, (add
320 def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
326 def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
334 def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
344 def GPRMM16MovePPairFirst : RegisterClass<"Mips", [i32], 32, (add
348 def GPRMM16MovePPairSecond : RegisterClass<"Mips", [i32], 32, (add
354 def GPR64 : RegisterClass<"Mips", [i64], 64, (add
368 def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
[all …]
H A DMipsCondMov.td55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
80 multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
88 multiclass MovzPats2<RegisterClass CRC, RegisterClass DRC,
95 multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td86 // 3. List caller-save register before callee-save regsiter in RegisterClass
545 def GR8 : RegisterClass<"X86", [i8], 8,
557 def GRH8 : RegisterClass<"X86", [i8], 8,
562 def GR16 : RegisterClass<"X86", [i16], 16,
569 def GRH16 : RegisterClass<"X86", [i16], 16,
574 def GR32 : RegisterClass<"X86", [i32], 32,
585 def GR64 : RegisterClass<"X86", [i64], 64,
592 def GR64PLTSafe : RegisterClass<"X86", [i64], 64,
598 def GR64_ArgRef: RegisterClass<"X86", [i64], 64, (add R10, R11)> {
604 def GR32_ArgRef: RegisterClass<"X86", [i32], 32, (add ECX, EDX)> {
[all …]
/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatternsV65.td9 multiclass vgathermh<RegisterClass RC> {
19 multiclass vgathermw<RegisterClass RC> {
29 multiclass vgathermhw<RegisterClass RC> {
43 multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
54 multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
65 multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
H A DHexagonRegisterInfo.td507 def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32, VecF16, VecF32], 512,
513 def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32, VecPF16, VecPF32], 1024,
519 def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 128,
525 def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048,
533 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
538 def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32,
542 def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32,
545 def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
548 def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64,
552 def PredRegs : RegisterClass<"Hexagon",
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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td227 def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
245 def GPRnoip : RegisterClass<"ARM", [i32], 32, (sub GPR, R12, LR)> {
262 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
274 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
283 def GPRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, PC)> {
293 def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
297 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {
305 def GPRwithZRnosp : RegisterClass<"ARM", [i32], 32, (sub GPRwithZR, SP)> {
318 def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)> {
324 def GPRlr : RegisterClass<"ARM", [i32], 32, (add LR)>;
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/src/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloatInstrFormats.td171 class FP_ALU_2R<bits<32> op, RegisterClass rc = FPR32>
174 class FP_ALU_3R<bits<32> op, RegisterClass rc = FPR32>
177 class FP_ALU_4R<bits<32> op, RegisterClass rc = FPR32>
183 class FP_CMP<bits<32> op, RegisterClass rc = FPR32>
186 class FP_CONV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
189 class FP_MOV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
192 class FP_SEL<bits<32> op, RegisterClass rc = FPR32>
205 class FP_LOAD_3R<bits<32> op, RegisterClass rc = FPR32>
208 class FP_LOAD_2RI12<bits<32> op, RegisterClass rc = FPR32>
214 class FP_STORE_3R<bits<32> op, RegisterClass rc = FPR32>
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H A DLoongArchRegisterInfo.td102 def GPR : RegisterClass<"LoongArch", [GRLenVT], 32, (add
120 def GPRT : RegisterClass<"LoongArch", [GRLenVT], 32, (add
170 def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
171 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
178 def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
188 def FCSR : RegisterClass<"LoongArch", [i32], 32, (sequence "FCSR%u", 0, 3)>;
196 def LSX128 : RegisterClass<"LoongArch",
206 def LASX256 : RegisterClass<"LoongArch",
216 def SCR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "SCR%u", 0, 3)>;
/src/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td114 def GPR8 : RegisterClass<"AVR", [i8], 8,
125 def GPR8lo : RegisterClass<"AVR", [i8], 8,
130 def LD8 : RegisterClass<"AVR", [i8], 8,
140 def LD8lo : RegisterClass<"AVR", [i8], 8,
144 def DREGS : RegisterClass<"AVR", [i16], 8,
159 : RegisterClass<"AVR", [i16], 8,
163 def DREGSLD8lo : RegisterClass<"AVR", [i16], 8,
171 def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
182 def DLDREGS : RegisterClass<"AVR", [i16], 8,
192 def IWREGS : RegisterClass<"AVR", [i16], 8,
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/src/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td152 def GPR : RegisterClass<"CSKY", [i32], 32,
162 def sGPR : RegisterClass<"CSKY", [i32], 32,
170 def mGPR : RegisterClass<"CSKY", [i32], 32,
176 def GPRSP : RegisterClass<"CSKY", [i32], 32, (add R14)> {
180 def GPRPair : RegisterClass<"CSKY", [untyped], 32, (add GPRTuple)> {
184 def CARRY : RegisterClass<"CSKY", [i32], 32, (add C)> {
191 def FPR32 : RegisterClass<"CSKY", [f32], 32,
193 def sFPR32 : RegisterClass<"CSKY", [f32], 32,
196 def FPR64 : RegisterClass<"CSKY", [f64], 32,
198 def sFPR64 : RegisterClass<"CSKY", [f64], 32,
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/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td155 def GPR32common : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 30)> {
159 def GPR64common : RegisterClass<"AArch64", [i64], 64,
166 def GPR32 : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WZR)> {
171 def GPR64 : RegisterClass<"AArch64", [i64], 64, (add GPR64common, XZR)> {
178 def GPR32sp : RegisterClass<"AArch64", [i32], 32, (add GPR32common, WSP)> {
183 def GPR64sp : RegisterClass<"AArch64", [i64], 64, (add GPR64common, SP)> {
189 def GPR32sponly : RegisterClass<"AArch64", [i32], 32, (add WSP)>;
190 def GPR64sponly : RegisterClass<"AArch64", [i64], 64, (add SP)>;
213 def GPR32arg : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 0, 7)>;
214 def GPR64arg : RegisterClass<"AArch64", [i64], 64, (sequence "X%u", 0, 7)>;
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/src/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrVec.td129 multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in,
139 multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> {
147 multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> {
156 multiclass VLDm<string opcStr, bits<8>opc, RegisterClass RC> {
198 multiclass VSTtgm<string opcStr, bits<8>opc, RegisterClass RC> {
207 multiclass VSTm<string opcStr, bits<8>opc, RegisterClass RC> {
234 multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
244 multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
254 multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
261 multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
[all …]
H A DVERegisterInfo.td77 def MISC : RegisterClass<"VE", [i64], 64,
95 def VLS : RegisterClass<"VE", [i32], 64, (add VL)>;
173 def I32 : RegisterClass<"VE", [i32], 32,
177 def I64 : RegisterClass<"VE", [i64, f64], 64,
181 def F32 : RegisterClass<"VE", [f32], 32,
185 def F128 : RegisterClass<"VE", [f128], 128,
190 def V64 : RegisterClass<"VE",
198 def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>;
199 def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>;
/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td342 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
349 def IntPair : RegisterClass<"SP", [v2i32], 64,
359 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
362 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
363 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>;
364 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>;
367 def LowDFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 15)>;
368 def LowQFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 7)>;
371 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
374 def GPROutgoingArg : RegisterClass<"SP", [i32, i64], 32, (sequence "O%u", 0, 5)>;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoDMR.td136 def DMRROWRC : RegisterClass<"PPC", [v128i1], 128,
141 def DMRROWpRC : RegisterClass<"PPC", [v256i1], 128,
146 def WACCRC : RegisterClass<"PPC", [v512i1], 128,
151 def WACC_HIRC : RegisterClass<"PPC", [v512i1], 128,
156 def DMRRC : RegisterClass<"PPC", [v1024i1], 128,
161 def DMRpRC : RegisterClass<"PPC", [v2048i1], 128,
H A DPPCRegisterInfo.td171 def VFHRC : RegisterClass<"PPC", [f64], 64, (sequence "VFH%u", 0, 31)>;
172 def FHRC : RegisterClass<"PPC", [f64], 64, (sequence "FH%u", 0, 31)>;
327 def GPRC32 : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "H%u", 2, 12),
334 def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
350 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
366 def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
377 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
388 def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12),
399 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
401 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
[all …]
/src/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DRegisterBank.td12 class RegisterBank<string name, list<RegisterClass> classes> {
14 list<RegisterClass> RegisterClasses = classes;
/src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td63 def GPR32: RegisterClass<"ARC", [i32], 32,
75 def SREG : RegisterClass<"ARC", [i32], 1, (add STATUS32)>;
77 def GPR_S : RegisterClass<"ARC", [i32], 8,
/src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td39 def GPR32 : RegisterClass<"BPF", [i32], 64, (add
46 def GPR : RegisterClass<"BPF", [i64], 64, (add
/src/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td44 def GRRegs : RegisterClass<"XCore", [i32], 32,
53 def RRegs : RegisterClass<"XCore", [i32], 32,
/src/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h57 const TargetRegisterClass *RegisterClass,
64 const TargetRegisterClass *RegisterClass,

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