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Searched refs:RegClass (Results 1 – 25 of 90) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td150 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
153 vti.LMul, vti.AVL, vti.RegClass,
166 vti.LMul, vti.AVL, vti.RegClass,
225 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
228 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
240 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
243 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
254 (fvti.Vector fvti.RegClass:$rs1))),
260 fvti.RegClass:$rs1,
270 (fvti.Vector fvti.RegClass:$rs1))),
[all …]
H A DRISCVInstrInfoVVLPatterns.td877 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
878 vti.RegClass, isSEWAware>;
881 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
894 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass,
908 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
909 vti.RegClass>;
912 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass,
928 vti.LMul, wti.RegClass, vti.RegClass>;
931 vti.Log2SEW, vti.LMul, wti.RegClass,
932 vti.RegClass>;
[all …]
H A DRISCVInstrInfoZvk.td576 def : Pat<(vti.Vector (op (vti.Vector vti.RegClass:$rs1))),
579 vti.RegClass:$rs1,
595 def : Pat<(vti.Vector (and (riscv_vnot vti.RegClass:$rs1),
596 vti.RegClass:$rs2)),
599 vti.RegClass:$rs2,
600 vti.RegClass:$rs1,
604 vti.RegClass:$rs2)),
607 vti.RegClass:$rs2,
644 def : Pat<(vti.Vector (rotl vti.RegClass:$rs2,
648 vti.RegClass:$rs2,
[all …]
H A DRISCVInstrInfoVPseudos.td261 VReg RegClass = M.vrclass;
964 class VPseudoNullaryNoMask<VReg RegClass> :
965 Pseudo<(outs RegClass:$rd),
966 (ins RegClass:$merge,
978 class VPseudoNullaryMask<VReg RegClass> :
979 Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
980 (ins GetVRegNoV0<RegClass>.R:$merge,
4609 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>;
4625 vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
4627 vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
[all …]
H A DRISCVInstrInfoXSf.td680 payload5, vti.RegClass, kind, op1_kind>;
684 vti.RegClass, kind, op1_kind>;
688 vti.RegClass, kind, op1_kind>;
697 wti.RegClass, vti.RegClass, kind, op1_kind>;
701 wti.RegClass, vti.RegClass, kind, op1_kind>;
705 wti.RegClass, vti.RegClass, kind, op1_kind>;
731 VdInfo.RegClass, VR, Vs2Info.RegClass>;
774 Vti.Log2SEW, Vti.RegClass,
775 Wti.RegClass, Wti.ScalarRegClass>;
785 defm : VPatVC_XV<"vv", "VV", vti, vti.Vector, vti.RegClass>;
[all …]
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrCMovSetCC.td18 def rr#suffix : ITy<0x40, MRMSrcRegCC, t, (outs t.RegClass:$dst),
19 (ins t.RegClass:$src1, t.RegClass:$src2, ccode:$cond),
21 [(set t.RegClass:$dst, (X86cmov t.RegClass:$src1,
22 … t.RegClass:$src2, timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
24 def rm#suffix : ITy<0x40, MRMSrcMemCC, t, (outs t.RegClass:$dst),
25 (ins t.RegClass:$src1, t.MemOperand:$src2, ccode:$cond),
27 [(set t.RegClass:$dst, (X86cmov t.RegClass:$src1,
34 def rr : ITy<0x40, MRMDestRegCC, t, (outs t.RegClass:$dst),
35 (ins t.RegClass:$src1, ccode:$cond),
37 [(set t.RegClass:$dst,
[all …]
H A DX86InstrUtils.td145 /// RegClass - This is the register class associated with this type. For
147 RegisterClass RegClass = regclass;
977 : ITy<o, MRMDestReg, t, out, (ins t.RegClass:$src1, t.RegClass:$src2), m,
982 [(set EFLAGS, (node t.RegClass:$src1, t.RegClass:$src2))]>,
992 (outs t.RegClass:$dst), []>, NDD<ndd>;
1001 (outs t.RegClass:$dst),
1002 [(set t.RegClass:$dst, EFLAGS,
1003 (node t.RegClass:$src1, t.RegClass:$src2))]>, DefEFLAGS, NDD<ndd>;
1012 : BinOpRR<o, m, !if(!eq(ndd, 0), binop_args, binop_ndd_args), t, (outs t.RegClass:$dst),
1013 [(set t.RegClass:$dst, EFLAGS,
[all …]
H A DX86InstrShiftRotate.td347 : ITy<o, MRMDestReg, t, (outs t.RegClass:$dst),
348 …(ins t.RegClass:$src1, t.RegClass:$src2, u8imm:$src3), m, !if(!eq(ndd, 0), triop_args, triop_ndd_a…
354 … [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, (i8 imm:$src3)))],
355 … [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, (i8 imm:$src3)))]);
359 …: BinOpRR<o, m, !if(!eq(ndd, 0), triop_cl_args, triop_cl_ndd_args), t, (outs t.RegClass:$dst), []>…
363 [(set t.RegClass:$dst, (node t.RegClass:$src1, t.RegClass:$src2, CL))],
364 [(set t.RegClass:$dst, (node t.RegClass:$src2, t.RegClass:$src1, CL))]);
368 : ITy<o, MRMDestMem, t, (outs), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
375 … [(store (node (t.LoadNode addr:$src1), t.RegClass:$src2, (i8 imm:$src3)), addr:$src1)],
376 … [(store (node t.RegClass:$src2, (t.LoadNode addr:$src1), (i8 imm:$src3)), addr:$src1)]);
[all …]
H A DX86InstrArithmetic.td264 (outs t.RegClass:$dst)> {
269 (outs t.RegClass:$dst), []> {
274 (outs t.RegClass:$dst),
275 [(set t.RegClass:$dst, EFLAGS, (X86smul_flag t.RegClass:$src1,
280 : BinOpMI8<"imul", binop_ndd_args, t, MRMSrcMem, (outs t.RegClass:$dst)> {
286 (outs t.RegClass:$dst), []> {
291 (outs t.RegClass:$dst),
292 [(set t.RegClass:$dst, EFLAGS, (X86smul_flag (t.LoadNode addr:$src1),
341 (outs t.RegClass:$dst)> {
346 (outs t.RegClass:$dst), []> {
[all …]
H A DX86InstrMisc.td1094 def rm#suffix : ITy<o, MRMSrcMem, t, (outs t.RegClass:$dst),
1096 [(set t.RegClass:$dst, (bswap (t.LoadNode addr:$src1)))]>,
1099 (ins t.MemOperand:$dst, t.RegClass:$src1),
1101 [(store (bswap t.RegClass:$src1), addr:$dst)]>,
1118 def rr : ITy<0x61, MRMDestReg, t, (outs t.RegClass:$dst),
1119 (ins t.RegClass:$src1), "movbe", unaryop_ndd_args,
1120 [(set t.RegClass:$dst, (bswap t.RegClass:$src1))]>,
1122 def rr_REV : ITy<0x60, MRMSrcReg, t, (outs t.RegClass:$dst),
1123 (ins t.RegClass:$src1), "movbe", unaryop_ndd_args, []>,
1164 def rr#suffix : ITy<o, MRMSrcReg, t, (outs t.RegClass:$dst),
[all …]
/src/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp104 if (MOI.RegClass == AVR::ZREGRegClassID) { in printOperand()
124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
126 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/src/contrib/llvm-project/llvm/lib/Target/SPIRV/MCTargetDesc/
H A DSPIRVMCCodeEmitter.cpp70 return (DefOpInfo.RegClass == SPIRV::IDRegClassID || in hasType()
71 DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) && in hasType()
72 FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID; in hasType()
/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPeephole.cpp98 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
99 CopyLocalOpc = WebAssembly::getCopyOpcodeForRegClass(RegClass); in maybeRewriteToFallthrough()
100 Register NewReg = MRI.createVirtualRegister(RegClass); in maybeRewriteToFallthrough()
H A DWebAssemblyRegStackify.cpp105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
106 if (RegClass == &WebAssembly::I32RegClass) { in convertImplicitDefToConstZero()
109 } else if (RegClass == &WebAssembly::I64RegClass) { in convertImplicitDefToConstZero()
112 } else if (RegClass == &WebAssembly::F32RegClass) { in convertImplicitDefToConstZero()
117 } else if (RegClass == &WebAssembly::F64RegClass) { in convertImplicitDefToConstZero()
122 } else if (RegClass == &WebAssembly::V128RegClass) { in convertImplicitDefToConstZero()
641 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
642 Register TeeReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
643 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse()
653 TII->get(getTeeOpcode(RegClass)), TeeReg) in moveAndTeeForMultiUse()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h46 std::unique_ptr<RCInfo[]> RegClass; variable
79 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp37 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
38 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
40 RI.RegClass = nullptr; in PhysicalRegisterInfo()
43 RI.RegClass = RC; in PhysicalRegisterInfo()
173 RI.RegClass ? RI.RegClass->LaneMask : LaneBitmask::getAll(); in mapTo()
H A DRegisterClassInfo.cpp51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
127 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp159 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
161 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
162 assert(RegClass->isAllocatable() && in createVirtualRegister()
167 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
/src/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h309 using RegClass = Bitfield::Element<unsigned, 16, 14>; variable
315 unsigned getRegClass() const { return Bitfield::get<RegClass>(Storage); } in getRegClass()
405 Bitfield::set<RegClass>(Storage, RC + 1); in setRegClass()
/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVRegisterBanks.td10 // as InstructionSelector RegClass checking code relies on them
/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1883 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
1884 Register TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1885 Register FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1950 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
1951 Register NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2010 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2011 Register PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2012 Register IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2124 const TargetRegisterClass *RegClass = in createEntryPHI() local
2126 Register NewBackedgeReg = MRI->createVirtualRegister(RegClass); in createEntryPHI()
[all …]
H A DGCNDPPCombine.cpp197 int16_t RegClass = MI.getDesc().operands()[Idx].RegClass; in getOperandSize() local
198 if (RegClass == -1) in getOperandSize()
202 return TRI->getRegSizeInBits(*TRI->getRegClass(RegClass)); in getOperandSize()
/src/contrib/llvm-project/llvm/utils/TableGen/
H A DCompressInstEmitter.cpp131 bool validateRegister(Record *Reg, Record *RegClass);
151 bool CompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister() argument
153 assert(RegClass->isSubClassOf("RegisterClass") && in validateRegister()
155 const CodeGenRegisterClass &RC = Target.getRegisterClass(RegClass); in validateRegister()
/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp562 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
743 (FrameReg.isVirtual() || RegClass->contains(FrameReg))) { in rewriteT2FrameIndex()
747 if (!MRI->constrainRegClass(FrameReg, RegClass)) in rewriteT2FrameIndex()
783 return Offset == 0 && (FrameReg.isVirtual() || RegClass->contains(FrameReg)); in rewriteT2FrameIndex()
/src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h97 const TargetRegisterClass &RegClass);
113 const TargetRegisterClass &RegClass,

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