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Searched refs:RSP (Results 1 – 25 of 30) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DFixupStatepointCallerSaved.cpp184 RegSlotPair RSP(Reg, FI); in recordReload() local
185 auto Res = Reloads[MBB].insert(RSP); in recordReload()
192 RegSlotPair RSP(Reg, FI); in hasReload() local
193 return Reloads.count(MBB) && Reloads[MBB].count(RSP); in hasReload()
246 for (auto &RSP : GlobalIndices[EHPad]) in reset() local
247 ReservedSlots.insert(RSP.second); in reset()
257 Vec, [Reg](RegSlotPair &RSP) { return Reg == RSP.first; }); in getFrameIndex() argument
/src/sys/amd64/amd64/
H A Dbpf_jit_machdep.c205 MOVrq(RSP, RBP); in bpf_jit_compile()
206 SUBib(BPF_MEMWORDS * sizeof(uint32_t), RSP); in bpf_jit_compile()
399 MOVobd(RSP, RSI, EAX); in bpf_jit_compile()
404 MOVobd(RSP, RSI, EDX); in bpf_jit_compile()
414 MOVomd(EAX, RSP, RSI); in bpf_jit_compile()
419 MOVomd(EDX, RSP, RSI); in bpf_jit_compile()
H A Dbpf_jit_machdep.h44 #define RSP 4 macro
/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrControl.td314 // RSP is marked as a use to prevent stack-pointer assignments that appear
317 let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
350 isCodeGenOnly = 1, Uses = [RSP, SSP] in {
384 Uses = [RSP, SSP],
405 Uses = [RSP, SSP],
424 let Uses = [RSP, EFLAGS, SSP] in {
H A DX86RegisterInfo.td288 def RSP : X86Reg<"rsp", 4, [ESP]>, DwarfRegNum<[7, -2, -2]>;
588 R30, R31, RBX, R14, R15, R12, R13, RBP, RSP, RIP)>;
590 // GR64PLTSafe - 64-bit GPRs without R10, R11, RSP and RIP. Could be used when
632 R8, R9, R11, RIP, RSP)>;
635 RIP, RSP)>;
653 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
679 // GR64_NOSP - GR64 registers except RSP (and RIP).
680 def GR64_NOSP : RegisterClass<"X86", [i64], 64, (sub GR64, RSP, RIP)>;
687 // GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
695 // GR64_NOREX2_NOSP - GR64_NOREX2 registers except RSP, RIP.
[all …]
H A DX86LoadValueInjectionRetHardening.cpp98 X86::RSP, false, 0) in runOnMachineFunction()
H A DX86FrameLowering.cpp994 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInlineWindowsCoreCLR64()
998 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false, in emitStackProbeInlineWindowsCoreCLR64()
1011 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP); in emitStackProbeInlineWindowsCoreCLR64()
1085 X86::RSP, false, RCXShadowSlot); in emitStackProbeInlineWindowsCoreCLR64()
1089 X86::RSP, false, RDXShadowSlot); in emitStackProbeInlineWindowsCoreCLR64()
1095 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP) in emitStackProbeInlineWindowsCoreCLR64()
1096 .addReg(X86::RSP) in emitStackProbeInlineWindowsCoreCLR64()
1164 unsigned SP = Uses64BitFramePtr ? X86::RSP : X86::ESP; in emitStackProbeCall()
1802 .addUse(X86::RSP) in emitPrologue()
1808 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64ri32), X86::RSP) in emitPrologue()
[all …]
H A DX86RegisterInfo.cpp68 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
550 for (const MCPhysReg &SubReg : subregs_inclusive(X86::RSP)) in getReservedRegs()
715 if (TRI.isSuperOrSubRegisterEq(X86::RSP, PhysReg)) in isFixedRegister()
1004 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP) in findDeadCallerSavedReg()
H A DX86IndirectThunks.cpp235 const Register SPReg = Is64Bit ? X86::RSP : X86::ESP; in populateThunk()
H A DX86SpeculativeLoadHardening.cpp1535 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP) in mergePredStateIntoSP()
1536 .addReg(X86::RSP) in mergePredStateIntoSP()
1553 .addReg(X86::RSP); in extractPredStateFromSP()
1582 } else if (BaseMO.getReg() == X86::RSP) { in hardenLoadAddr()
2144 .addReg(/*Base*/ X86::RSP) in tracePredStateThroughCall()
H A DX86InstrMisc.td45 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
122 let Uses = [RSP] in
135 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in
155 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
200 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
210 let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
213 let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in
H A DX86InstrCompiler.td52 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
57 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP], SchedRW = [WriteALU] in {
113 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
130 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
157 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
483 // All calls clobber the non-callee saved registers. RSP is marked as
492 usesCustomInserter = 1, Uses = [RSP, SSP] in {
514 let Defs = [EAX, EFLAGS], usesCustomInserter = 1, Uses = [RSP, SSP] in {
539 Uses = [RSP, SSP],
H A DX86InstrOperands.td9 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for
H A DX86FixupLEAs.cpp570 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
H A DX86InstrSystem.td73 let hasSideEffects = 1, Defs = [RSP, EFLAGS] in {
78 } // hasSideEffects = 1, Defs = [RSP, EFLAGS]
H A DX86InstrInfo.cpp10566 if (MI.modifiesRegister(X86::RSP, &RI) || MI.readsRegister(X86::RSP, &RI) || in getOutliningTypeImpl()
10567 MI.getDesc().hasImplicitUseOfPhysReg(X86::RSP) || in getOutliningTypeImpl()
10568 MI.getDesc().hasImplicitDefOfPhysReg(X86::RSP)) in getOutliningTypeImpl()
/src/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp263 {codeview::RegisterId::RSP, X86::RSP}, in initLLVMToSEHAndCVRegMapping()
468 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; in createX86MCAsmInfo()
787 #define SP_SUB_SUPER(R) SUB_SUPER(SPL, SP, ESP, RSP, R) in getX86SubSuperRegister()
925 SP_SUB_SUPER(RSP) in getX86SubSuperRegister()
H A DX86BaseInfo.h1335 case X86::RSP: in needSIB()
H A DX86MCCodeEmitter.cpp827 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && in emitMemModRMByte()
/src/contrib/llvm-project/llvm/lib/DebugInfo/CodeView/
H A DSymbolRecordMapping.cpp524 case EncodedFramePtrReg::StackPtr: return RegisterId::RSP; in decodeFramePtrReg()
559 case RegisterId::RSP: in encodeFramePtrReg()
/src/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DCodeViewRegisterMapping.cpp718 case llvm::codeview::RegisterId::RSP: in GetRegisterSize()
/src/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h326 ENTRY(RSP) \
/src/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def227 CV_REGISTER(RSP, 335)
/src/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp1333 IndexReg == X86::ESP || IndexReg == X86::RSP) { in CheckBaseRegAndIndexRegAndScale()
2662 if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP && in parseIntelOperand()
2663 (IndexReg == X86::ESP || IndexReg == X86::RSP)) in parseIntelOperand()
3956 is64BitMode() ? X86::RSP : (Parse32 ? X86::ESP : X86::SP); in applyLVICFIMitigation()
/src/crypto/openssl/Configurations/
H A Dwindows-makefile.tmpl722 # in handling quoted paths: https://quality.embarcadero.com/browse/RSP-31756

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