1/*- 2 * Copyright (C) 2006-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com> 3 * Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com> 4 * Copyright (C) 2006 Juniper Networks, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29/*- 30 * Copyright (C) 1995, 1996 Wolfgang Solfrank. 31 * Copyright (C) 1995, 1996 TooLs GmbH. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 3. All advertising materials mentioning features or use of this software 43 * must display the following acknowledgement: 44 * This product includes software developed by TooLs GmbH. 45 * 4. The name of TooLs GmbH may not be used to endorse or promote products 46 * derived from this software without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 * 59 * from: $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ 60 */ 61 62/* 63 * NOTICE: This is not a standalone file. to use it, #include it in 64 * your port's locore.S, like so: 65 * 66 * #include <powerpc/booke/trap_subr.S> 67 */ 68 69/* 70 * SPRG usage notes 71 * 72 * SPRG0 - pcpu pointer 73 * SPRG1 - all interrupts except TLB miss, critical, machine check 74 * SPRG2 - critical 75 * SPRG3 - machine check 76 * SPRG4-6 - scratch 77 * 78 */ 79 80/* Get the per-CPU data structure */ 81#define GET_CPUINFO(r) mfsprg0 r 82 83#define RES_GRANULE 64 84#define RES_LOCK 0 /* offset to the 'lock' word */ 85#ifdef __powerpc64__ 86#define RES_RECURSE 8 /* offset to the 'recurse' word */ 87#else 88#define RES_RECURSE 4 /* offset to the 'recurse' word */ 89#endif 90 91/* 92 * Standard interrupt prolog 93 * 94 * sprg_sp - SPRG{1-3} reg used to temporarily store the SP 95 * savearea - temp save area (pc_{tempsave, disisave, critsave, mchksave}) 96 * isrr0-1 - save restore registers with CPU state at interrupt time (may be 97 * SRR0-1, CSRR0-1, MCSRR0-1 98 * 99 * 1. saves in the given savearea: 100 * - R30-31 101 * - DEAR, ESR 102 * - xSRR0-1 103 * 104 * 2. saves CR -> R30 105 * 106 * 3. switches to kstack if needed 107 * 108 * 4. notes: 109 * - R31 can be used as scratch register until a new frame is laid on 110 * the stack with FRAME_SETUP 111 * 112 * - potential TLB miss: NO. Saveareas are always acessible via TLB1 113 * permanent entries, and within this prolog we do not dereference any 114 * locations potentially not in the TLB 115 */ 116#define STANDARD_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 117 mtspr sprg_sp, %r1; /* Save SP */ \ 118 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 119 STORE %r30, (savearea+CPUSAVE_R30)(%r1); \ 120 STORE %r31, (savearea+CPUSAVE_R31)(%r1); \ 121 mfspr %r30, SPR_DEAR; \ 122 mfspr %r31, SPR_ESR; \ 123 STORE %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 124 STORE %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 125 mfspr %r30, isrr0; \ 126 mfspr %r31, isrr1; /* MSR at interrupt time */ \ 127 STORE %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 128 STORE %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 129 isync; \ 130 mfspr %r1, sprg_sp; /* Restore SP */ \ 131 mfcr %r30; /* Save CR */ \ 132 /* switch to per-thread kstack if intr taken in user mode */ \ 133 mtcr %r31; /* MSR at interrupt time */ \ 134 bf 17, 1f; \ 135 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 136 LOAD %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 1371: 138 139#define STANDARD_CRIT_PROLOG(sprg_sp, savearea, isrr0, isrr1) \ 140 mtspr sprg_sp, %r1; /* Save SP */ \ 141 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 142 STORE %r30, (savearea+CPUSAVE_R30)(%r1); \ 143 STORE %r31, (savearea+CPUSAVE_R31)(%r1); \ 144 mfspr %r30, SPR_DEAR; \ 145 mfspr %r31, SPR_ESR; \ 146 STORE %r30, (savearea+CPUSAVE_BOOKE_DEAR)(%r1); \ 147 STORE %r31, (savearea+CPUSAVE_BOOKE_ESR)(%r1); \ 148 mfspr %r30, isrr0; \ 149 mfspr %r31, isrr1; /* MSR at interrupt time */ \ 150 STORE %r30, (savearea+CPUSAVE_SRR0)(%r1); \ 151 STORE %r31, (savearea+CPUSAVE_SRR1)(%r1); \ 152 mfspr %r30, SPR_SRR0; \ 153 mfspr %r31, SPR_SRR1; /* MSR at interrupt time */ \ 154 STORE %r30, (savearea+BOOKE_CRITSAVE_SRR0)(%r1); \ 155 STORE %r31, (savearea+BOOKE_CRITSAVE_SRR1)(%r1); \ 156 isync; \ 157 mfspr %r1, sprg_sp; /* Restore SP */ \ 158 mfcr %r30; /* Save CR */ \ 159 /* switch to per-thread kstack if intr taken in user mode */ \ 160 mtcr %r31; /* MSR at interrupt time */ \ 161 bf 17, 1f; \ 162 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 163 LOAD %r1, PC_CURPCB(%r1); /* Per-thread kernel stack */ \ 1641: 165 166/* 167 * FRAME_SETUP assumes: 168 * SPRG{1-3} SP at the time interrupt occurred 169 * savearea r30-r31, DEAR, ESR, xSRR0-1 170 * r30 CR 171 * r31 scratch 172 * r1 kernel stack 173 * 174 * sprg_sp - SPRG reg containing SP at the time interrupt occurred 175 * savearea - temp save 176 * exc - exception number (EXC_xxx) 177 * 178 * 1. sets a new frame 179 * 2. saves in the frame: 180 * - R0, R1 (SP at the time of interrupt), R2, LR, CR 181 * - R3-31 (R30-31 first restored from savearea) 182 * - XER, CTR, DEAR, ESR (from savearea), xSRR0-1 183 * 184 * Notes: 185 * - potential TLB miss: YES, since we make dereferences to kstack, which 186 * can happen not covered (we can have up to two DTLB misses if fortunate 187 * enough i.e. when kstack crosses page boundary and both pages are 188 * untranslated) 189 */ 190#ifdef __powerpc64__ 191#define SAVE_REGS(r) \ 192 std %r3, FRAME_3+CALLSIZE(r); \ 193 std %r4, FRAME_4+CALLSIZE(r); \ 194 std %r5, FRAME_5+CALLSIZE(r); \ 195 std %r6, FRAME_6+CALLSIZE(r); \ 196 std %r7, FRAME_7+CALLSIZE(r); \ 197 std %r8, FRAME_8+CALLSIZE(r); \ 198 std %r9, FRAME_9+CALLSIZE(r); \ 199 std %r10, FRAME_10+CALLSIZE(r); \ 200 std %r11, FRAME_11+CALLSIZE(r); \ 201 std %r12, FRAME_12+CALLSIZE(r); \ 202 std %r13, FRAME_13+CALLSIZE(r); \ 203 std %r14, FRAME_14+CALLSIZE(r); \ 204 std %r15, FRAME_15+CALLSIZE(r); \ 205 std %r16, FRAME_16+CALLSIZE(r); \ 206 std %r17, FRAME_17+CALLSIZE(r); \ 207 std %r18, FRAME_18+CALLSIZE(r); \ 208 std %r19, FRAME_19+CALLSIZE(r); \ 209 std %r20, FRAME_20+CALLSIZE(r); \ 210 std %r21, FRAME_21+CALLSIZE(r); \ 211 std %r22, FRAME_22+CALLSIZE(r); \ 212 std %r23, FRAME_23+CALLSIZE(r); \ 213 std %r24, FRAME_24+CALLSIZE(r); \ 214 std %r25, FRAME_25+CALLSIZE(r); \ 215 std %r26, FRAME_26+CALLSIZE(r); \ 216 std %r27, FRAME_27+CALLSIZE(r); \ 217 std %r28, FRAME_28+CALLSIZE(r); \ 218 std %r29, FRAME_29+CALLSIZE(r); \ 219 std %r30, FRAME_30+CALLSIZE(r); \ 220 std %r31, FRAME_31+CALLSIZE(r) 221#define LD_REGS(r) \ 222 ld %r3, FRAME_3+CALLSIZE(r); \ 223 ld %r4, FRAME_4+CALLSIZE(r); \ 224 ld %r5, FRAME_5+CALLSIZE(r); \ 225 ld %r6, FRAME_6+CALLSIZE(r); \ 226 ld %r7, FRAME_7+CALLSIZE(r); \ 227 ld %r8, FRAME_8+CALLSIZE(r); \ 228 ld %r9, FRAME_9+CALLSIZE(r); \ 229 ld %r10, FRAME_10+CALLSIZE(r); \ 230 ld %r11, FRAME_11+CALLSIZE(r); \ 231 ld %r12, FRAME_12+CALLSIZE(r); \ 232 ld %r13, FRAME_13+CALLSIZE(r); \ 233 ld %r14, FRAME_14+CALLSIZE(r); \ 234 ld %r15, FRAME_15+CALLSIZE(r); \ 235 ld %r16, FRAME_16+CALLSIZE(r); \ 236 ld %r17, FRAME_17+CALLSIZE(r); \ 237 ld %r18, FRAME_18+CALLSIZE(r); \ 238 ld %r19, FRAME_19+CALLSIZE(r); \ 239 ld %r20, FRAME_20+CALLSIZE(r); \ 240 ld %r21, FRAME_21+CALLSIZE(r); \ 241 ld %r22, FRAME_22+CALLSIZE(r); \ 242 ld %r23, FRAME_23+CALLSIZE(r); \ 243 ld %r24, FRAME_24+CALLSIZE(r); \ 244 ld %r25, FRAME_25+CALLSIZE(r); \ 245 ld %r26, FRAME_26+CALLSIZE(r); \ 246 ld %r27, FRAME_27+CALLSIZE(r); \ 247 ld %r28, FRAME_28+CALLSIZE(r); \ 248 ld %r29, FRAME_29+CALLSIZE(r); \ 249 ld %r30, FRAME_30+CALLSIZE(r); \ 250 ld %r31, FRAME_31+CALLSIZE(r) 251#else 252#define SAVE_REGS(r) \ 253 stmw %r3, FRAME_3+CALLSIZE(r) 254#define LD_REGS(r) \ 255 lmw %r3, FRAME_3+CALLSIZE(r) 256#endif 257#define FRAME_SETUP(sprg_sp, savearea, exc) \ 258 mfspr %r31, sprg_sp; /* get saved SP */ \ 259 /* establish a new stack frame and put everything on it */ \ 260 STU %r31, -(FRAMELEN+REDZONE)(%r1); \ 261 STORE %r0, FRAME_0+CALLSIZE(%r1); /* save r0 in the trapframe */ \ 262 STORE %r31, FRAME_1+CALLSIZE(%r1); /* save SP " " */ \ 263 STORE %r2, FRAME_2+CALLSIZE(%r1); /* save r2 " " */ \ 264 mflr %r31; \ 265 STORE %r31, FRAME_LR+CALLSIZE(%r1); /* save LR " " */ \ 266 STORE %r30, FRAME_CR+CALLSIZE(%r1); /* save CR " " */ \ 267 GET_CPUINFO(%r2); \ 268 LOAD %r30, (savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \ 269 LOAD %r31, (savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \ 270 /* save R3-31 */ \ 271 SAVE_REGS(%r1); \ 272 /* save DEAR, ESR */ \ 273 LOAD %r28, (savearea+CPUSAVE_BOOKE_DEAR)(%r2); \ 274 LOAD %r29, (savearea+CPUSAVE_BOOKE_ESR)(%r2); \ 275 STORE %r28, FRAME_BOOKE_DEAR+CALLSIZE(%r1); \ 276 STORE %r29, FRAME_BOOKE_ESR+CALLSIZE(%r1); \ 277 /* save XER, CTR, exc number */ \ 278 mfxer %r3; \ 279 mfctr %r4; \ 280 STORE %r3, FRAME_XER+CALLSIZE(%r1); \ 281 STORE %r4, FRAME_CTR+CALLSIZE(%r1); \ 282 li %r5, exc; \ 283 STORE %r5, FRAME_EXC+CALLSIZE(%r1); \ 284 /* save DBCR0 */ \ 285 mfspr %r3, SPR_DBCR0; \ 286 STORE %r3, FRAME_BOOKE_DBCR0+CALLSIZE(%r1); \ 287 /* save xSSR0-1 */ \ 288 LOAD %r30, (savearea+CPUSAVE_SRR0)(%r2); \ 289 LOAD %r31, (savearea+CPUSAVE_SRR1)(%r2); \ 290 STORE %r30, FRAME_SRR0+CALLSIZE(%r1); \ 291 STORE %r31, FRAME_SRR1+CALLSIZE(%r1); \ 292 LOAD THREAD_REG, PC_CURTHREAD(%r2); \ 293 294/* 295 * 296 * isrr0-1 - save restore registers to restore CPU state to (may be 297 * SRR0-1, CSRR0-1, MCSRR0-1 298 * 299 * Notes: 300 * - potential TLB miss: YES. The deref'd kstack may be not covered 301 */ 302#define FRAME_LEAVE(isrr0, isrr1) \ 303 wrteei 0; \ 304 /* restore CTR, XER, LR, CR */ \ 305 LOAD %r4, FRAME_CTR+CALLSIZE(%r1); \ 306 LOAD %r5, FRAME_XER+CALLSIZE(%r1); \ 307 LOAD %r6, FRAME_LR+CALLSIZE(%r1); \ 308 LOAD %r7, FRAME_CR+CALLSIZE(%r1); \ 309 mtctr %r4; \ 310 mtxer %r5; \ 311 mtlr %r6; \ 312 mtcr %r7; \ 313 /* restore DBCR0 */ \ 314 LOAD %r4, FRAME_BOOKE_DBCR0+CALLSIZE(%r1); \ 315 mtspr SPR_DBCR0, %r4; \ 316 /* restore xSRR0-1 */ \ 317 LOAD %r30, FRAME_SRR0+CALLSIZE(%r1); \ 318 LOAD %r31, FRAME_SRR1+CALLSIZE(%r1); \ 319 mtspr isrr0, %r30; \ 320 mtspr isrr1, %r31; \ 321 /* restore R2-31, SP */ \ 322 LD_REGS(%r1); \ 323 LOAD %r2, FRAME_2+CALLSIZE(%r1); \ 324 LOAD %r0, FRAME_0+CALLSIZE(%r1); \ 325 LOAD %r1, FRAME_1+CALLSIZE(%r1); \ 326 isync 327 328/* 329 * TLB miss prolog 330 * 331 * saves LR, CR, SRR0-1, R20-31 in the TLBSAVE area 332 * 333 * Notes: 334 * - potential TLB miss: NO. It is crucial that we do not generate a TLB 335 * miss within the TLB prolog itself! 336 * - TLBSAVE is always translated 337 */ 338#ifdef __powerpc64__ 339#define TLB_SAVE_REGS(br) \ 340 std %r20, (TLBSAVE_BOOKE_R20)(br); \ 341 std %r21, (TLBSAVE_BOOKE_R21)(br); \ 342 std %r22, (TLBSAVE_BOOKE_R22)(br); \ 343 std %r23, (TLBSAVE_BOOKE_R23)(br); \ 344 std %r24, (TLBSAVE_BOOKE_R24)(br); \ 345 std %r25, (TLBSAVE_BOOKE_R25)(br); \ 346 std %r26, (TLBSAVE_BOOKE_R26)(br); \ 347 std %r27, (TLBSAVE_BOOKE_R27)(br); \ 348 std %r28, (TLBSAVE_BOOKE_R28)(br); \ 349 std %r29, (TLBSAVE_BOOKE_R29)(br); \ 350 std %r30, (TLBSAVE_BOOKE_R30)(br); \ 351 std %r31, (TLBSAVE_BOOKE_R31)(br); 352#define TLB_RESTORE_REGS(br) \ 353 ld %r20, (TLBSAVE_BOOKE_R20)(br); \ 354 ld %r21, (TLBSAVE_BOOKE_R21)(br); \ 355 ld %r22, (TLBSAVE_BOOKE_R22)(br); \ 356 ld %r23, (TLBSAVE_BOOKE_R23)(br); \ 357 ld %r24, (TLBSAVE_BOOKE_R24)(br); \ 358 ld %r25, (TLBSAVE_BOOKE_R25)(br); \ 359 ld %r26, (TLBSAVE_BOOKE_R26)(br); \ 360 ld %r27, (TLBSAVE_BOOKE_R27)(br); \ 361 ld %r28, (TLBSAVE_BOOKE_R28)(br); \ 362 ld %r29, (TLBSAVE_BOOKE_R29)(br); \ 363 ld %r30, (TLBSAVE_BOOKE_R30)(br); \ 364 ld %r31, (TLBSAVE_BOOKE_R31)(br); 365#define TLB_NEST(outr,inr) \ 366 rlwinm outr, inr, 7, 23, 24; /* 8 x TLBSAVE_LEN */ 367#else 368#define TLB_SAVE_REGS(br) \ 369 stmw %r20, TLBSAVE_BOOKE_R20(br) 370#define TLB_RESTORE_REGS(br) \ 371 lmw %r20, TLBSAVE_BOOKE_R20(br) 372#define TLB_NEST(outr,inr) \ 373 rlwinm outr, inr, 6, 24, 25; /* 4 x TLBSAVE_LEN */ 374#endif 375#define TLB_PROLOG \ 376 mtspr SPR_SPRG4, %r1; /* Save SP */ \ 377 mtspr SPR_SPRG5, %r28; \ 378 mtspr SPR_SPRG6, %r29; \ 379 /* calculate TLB nesting level and TLBSAVE instance address */ \ 380 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 381 LOAD %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 382 TLB_NEST(%r29,%r28); \ 383 addi %r28, %r28, 1; \ 384 STORE %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 385 addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 386 add %r1, %r1, %r29; /* current TLBSAVE ptr */ \ 387 \ 388 /* save R20-31 */ \ 389 mfspr %r28, SPR_SPRG5; \ 390 mfspr %r29, SPR_SPRG6; \ 391 TLB_SAVE_REGS(%r1); \ 392 /* save LR, CR */ \ 393 mflr %r30; \ 394 mfcr %r31; \ 395 STORE %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 396 STORE %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 397 /* save SRR0-1 */ \ 398 mfsrr0 %r30; /* execution addr at interrupt time */ \ 399 mfsrr1 %r31; /* MSR at interrupt time*/ \ 400 STORE %r30, (TLBSAVE_BOOKE_SRR0)(%r1); /* save SRR0 */ \ 401 STORE %r31, (TLBSAVE_BOOKE_SRR1)(%r1); /* save SRR1 */ \ 402 isync; \ 403 mfspr %r1, SPR_SPRG4 404 405/* 406 * restores LR, CR, SRR0-1, R20-31 from the TLBSAVE area 407 * 408 * same notes as for the TLB_PROLOG 409 */ 410#define TLB_RESTORE \ 411 mtspr SPR_SPRG4, %r1; /* Save SP */ \ 412 GET_CPUINFO(%r1); /* Per-cpu structure */ \ 413 /* calculate TLB nesting level and TLBSAVE instance addr */ \ 414 LOAD %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 415 subi %r28, %r28, 1; \ 416 STORE %r28, PC_BOOKE_TLB_LEVEL(%r1); \ 417 TLB_NEST(%r29,%r28); \ 418 addi %r29, %r29, PC_BOOKE_TLBSAVE@l; \ 419 add %r1, %r1, %r29; \ 420 \ 421 /* restore LR, CR */ \ 422 LOAD %r30, (TLBSAVE_BOOKE_LR)(%r1); \ 423 LOAD %r31, (TLBSAVE_BOOKE_CR)(%r1); \ 424 mtlr %r30; \ 425 mtcr %r31; \ 426 /* restore SRR0-1 */ \ 427 LOAD %r30, (TLBSAVE_BOOKE_SRR0)(%r1); \ 428 LOAD %r31, (TLBSAVE_BOOKE_SRR1)(%r1); \ 429 mtsrr0 %r30; \ 430 mtsrr1 %r31; \ 431 /* restore R20-31 */ \ 432 TLB_RESTORE_REGS(%r1); \ 433 mfspr %r1, SPR_SPRG4 434 435#ifdef SMP 436#define TLB_LOCK \ 437 GET_CPUINFO(%r20); \ 438 LOAD %r21, PC_CURTHREAD(%r20); \ 439 LOAD %r22, PC_BOOKE_TLB_LOCK(%r20); \ 440 \ 4411: LOADX %r23, 0, %r22; \ 442 CMPI %r23, TLB_UNLOCKED; \ 443 beq 2f; \ 444 \ 445 /* check if this is recursion */ \ 446 CMPL cr0, %r21, %r23; \ 447 bne- 1b; \ 448 \ 4492: /* try to acquire lock */ \ 450 STOREX %r21, 0, %r22; \ 451 bne- 1b; \ 452 \ 453 /* got it, update recursion counter */ \ 454 lwz %r21, RES_RECURSE(%r22); \ 455 addi %r21, %r21, 1; \ 456 stw %r21, RES_RECURSE(%r22); \ 457 isync; \ 458 msync 459 460#define TLB_UNLOCK \ 461 GET_CPUINFO(%r20); \ 462 LOAD %r21, PC_CURTHREAD(%r20); \ 463 LOAD %r22, PC_BOOKE_TLB_LOCK(%r20); \ 464 \ 465 /* update recursion counter */ \ 466 lwz %r23, RES_RECURSE(%r22); \ 467 subi %r23, %r23, 1; \ 468 stw %r23, RES_RECURSE(%r22); \ 469 \ 470 cmplwi %r23, 0; \ 471 bne 1f; \ 472 isync; \ 473 msync; \ 474 \ 475 /* release the lock */ \ 476 li %r23, TLB_UNLOCKED; \ 477 STORE %r23, 0(%r22); \ 4781: isync; \ 479 msync 480#else 481#define TLB_LOCK 482#define TLB_UNLOCK 483#endif /* SMP */ 484 485#define INTERRUPT(label) \ 486 .globl label; \ 487 .align 5; \ 488 CNAME(label): 489 490/* 491 * Interrupt handling routines in BookE can be flexibly placed and do not have 492 * to live in pre-defined vectors location. Note they need to be TLB-mapped at 493 * all times in order to be able to handle exceptions. We thus arrange for 494 * them to be part of kernel text which is always TLB-accessible. 495 * 496 * The interrupt handling routines have to be 16 bytes aligned: we align them 497 * to 32 bytes (cache line length) which supposedly performs better. 498 * 499 */ 500 .text 501 .globl CNAME(interrupt_vector_base) 502 .align 5 503interrupt_vector_base: 504/***************************************************************************** 505 * Catch-all handler to handle uninstalled IVORs 506 ****************************************************************************/ 507INTERRUPT(int_unknown) 508 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 509 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_RSVD) 510 b trap_common 511 512/***************************************************************************** 513 * Critical input interrupt 514 ****************************************************************************/ 515INTERRUPT(int_critical_input) 516 STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 517 FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_CRIT) 518 GET_TOCBASE(%r2) 519 addi %r3, %r1, CALLSIZE 520 bl CNAME(powerpc_interrupt) 521 TOC_RESTORE 522 FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 523 rfci 524 525 526/***************************************************************************** 527 * Machine check interrupt 528 ****************************************************************************/ 529INTERRUPT(int_machine_check) 530 STANDARD_PROLOG(SPR_SPRG3, PC_BOOKE_MCHKSAVE, SPR_MCSRR0, SPR_MCSRR1) 531 FRAME_SETUP(SPR_SPRG3, PC_BOOKE_MCHKSAVE, EXC_MCHK) 532 GET_TOCBASE(%r2) 533 addi %r3, %r1, CALLSIZE 534 bl CNAME(powerpc_interrupt) 535 TOC_RESTORE 536 FRAME_LEAVE(SPR_MCSRR0, SPR_MCSRR1) 537 rfmci 538 539 540/***************************************************************************** 541 * Data storage interrupt 542 ****************************************************************************/ 543INTERRUPT(int_data_storage) 544 STANDARD_PROLOG(SPR_SPRG1, PC_DISISAVE, SPR_SRR0, SPR_SRR1) 545 FRAME_SETUP(SPR_SPRG1, PC_DISISAVE, EXC_DSI) 546 b trap_common 547 548 549/***************************************************************************** 550 * Instruction storage interrupt 551 ****************************************************************************/ 552INTERRUPT(int_instr_storage) 553 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 554 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ISI) 555 b trap_common 556 557 558/***************************************************************************** 559 * External input interrupt 560 ****************************************************************************/ 561INTERRUPT(int_external_input) 562 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 563 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_EXI) 564 b trap_common 565 566 567INTERRUPT(int_alignment) 568 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 569 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_ALI) 570 b trap_common 571 572 573INTERRUPT(int_program) 574 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 575 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_PGM) 576 b trap_common 577 578 579INTERRUPT(int_fpu) 580 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 581 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_FPU) 582 b trap_common 583 584 585/***************************************************************************** 586 * System call 587 ****************************************************************************/ 588INTERRUPT(int_syscall) 589 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 590 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_SC) 591 b trap_common 592 593 594/***************************************************************************** 595 * Decrementer interrupt 596 ****************************************************************************/ 597INTERRUPT(int_decrementer) 598 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 599 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_DECR) 600 b trap_common 601 602 603/***************************************************************************** 604 * Fixed interval timer 605 ****************************************************************************/ 606INTERRUPT(int_fixed_interval_timer) 607 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 608 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_FIT) 609 b trap_common 610 611 612/***************************************************************************** 613 * Watchdog interrupt 614 ****************************************************************************/ 615INTERRUPT(int_watchdog) 616 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 617 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_WDOG) 618 b trap_common 619 620 621/***************************************************************************** 622 * Altivec Unavailable interrupt 623 ****************************************************************************/ 624INTERRUPT(int_vec) 625 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 626 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_VEC) 627 b trap_common 628 629 630/***************************************************************************** 631 * Altivec Assist interrupt 632 ****************************************************************************/ 633INTERRUPT(int_vecast) 634 STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 635 FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_VECAST_E) 636 b trap_common 637 638 639#ifdef HWPMC_HOOKS 640/***************************************************************************** 641 * PMC Interrupt 642 ****************************************************************************/ 643INTERRUPT(int_performance_counter) 644 STANDARD_PROLOG(SPR_SPRG3, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) 645 FRAME_SETUP(SPR_SPRG3, PC_TEMPSAVE, EXC_PERF) 646 b trap_common 647#endif 648 649 650/***************************************************************************** 651 * Data TLB miss interrupt 652 * 653 * There can be nested TLB misses - while handling a TLB miss we reference 654 * data structures that may be not covered by translations. We support up to 655 * TLB_NESTED_MAX-1 nested misses. 656 * 657 * Registers use: 658 * r31 - dear 659 * r30 - unused 660 * r29 - saved mas0 661 * r28 - saved mas1 662 * r27 - saved mas2 663 * r26 - pmap address 664 * r25 - pte address 665 * 666 * r20:r23 - scratch registers 667 ****************************************************************************/ 668INTERRUPT(int_data_tlb_error) 669 TLB_PROLOG 670 TLB_LOCK 671 672 mfspr %r31, SPR_DEAR 673 674 /* 675 * Save MAS0-MAS2 registers. There might be another tlb miss during 676 * pte lookup overwriting current contents (which was hw filled). 677 */ 678 mfspr %r29, SPR_MAS0 679 mfspr %r28, SPR_MAS1 680 mfspr %r27, SPR_MAS2 681 682 /* Check faulting address. */ 683 LOAD_ADDR(%r21, VM_MAXUSER_ADDRESS) 684 CMPL cr0, %r31, %r21 685 blt search_user_pmap 686 687 /* If it's kernel address, allow only supervisor mode misses. */ 688 mfsrr1 %r21 689 mtcr %r21 690 bt 17, search_failed /* check MSR[PR] */ 691 692#ifdef __powerpc64__ 693 srdi %r21, %r31, 48 694 cmpldi cr0, %r21, VM_MIN_KERNEL_ADDRESS@highest 695#else 696 lis %r21, VM_MIN_KERNEL_ADDRESS@h 697 cmplw cr0, %r31, %r21 698#endif 699 blt search_failed 700 701search_kernel_pmap: 702 /* Load r26 with kernel_pmap address */ 703 bl 1f 704#ifdef __powerpc64__ 705 .llong kernel_pmap_store-. 706#else 707 .long kernel_pmap_store-. 708#endif 7091: mflr %r21 710 LOAD %r26, 0(%r21) 711 add %r26, %r21, %r26 /* kernel_pmap_store in r26 */ 712 713 /* Force kernel tid, set TID to 0 in MAS1. */ 714 li %r21, 0 715 rlwimi %r28, %r21, 0, 8, 15 /* clear TID bits */ 716 717tlb_miss_handle: 718 /* This may result in nested tlb miss. */ 719 bl pte_lookup /* returns PTE address in R25 */ 720 721 CMPI %r25, 0 /* pte found? */ 722 beq search_failed 723 724 /* Finish up, write TLB entry. */ 725 bl tlb_fill_entry 726 727tlb_miss_return: 728 TLB_UNLOCK 729 TLB_RESTORE 730 rfi 731 732search_user_pmap: 733 /* Load r26 with current user space process pmap */ 734 GET_CPUINFO(%r26) 735 LOAD %r26, PC_CURPMAP(%r26) 736 737 b tlb_miss_handle 738 739search_failed: 740 /* 741 * Whenever we don't find a TLB mapping in PT, set a TLB0 entry with 742 * the faulting virtual address anyway, but put a fake RPN and no 743 * access rights. This should cause a following {D,I}SI exception. 744 */ 745 lis %r23, 0xffff0000@h /* revoke all permissions */ 746 747 /* Load MAS registers. */ 748 mtspr SPR_MAS0, %r29 749 mtspr SPR_MAS1, %r28 750 mtspr SPR_MAS2, %r27 751 mtspr SPR_MAS3, %r23 752 753 li %r23, 0 754 mtspr SPR_MAS7, %r23 755 756 isync 757 tlbwe 758 msync 759 isync 760 b tlb_miss_return 761 762/***************************************************************************** 763 * 764 * Return pte address that corresponds to given pmap/va. If there is no valid 765 * entry return 0. 766 * 767 * input: r26 - pmap 768 * input: r31 - dear 769 * output: r25 - pte address 770 * 771 * scratch regs used: r21 772 * 773 ****************************************************************************/ 774pte_lookup: 775 CMPI %r26, 0 776 beq 1f /* fail quickly if pmap is invalid */ 777 778#ifdef __powerpc64__ 779 rldicl %r21, %r31, (64 - PG_ROOT_L), (64 - PG_ROOT_NUM) /* pp2d offset */ 780 slwi %r21, %r21, PG_ROOT_ENTRY_SHIFT /* multiply by pp2d entry size */ 781 ld %r25, PM_ROOT(%r26) /* pmap pm_pp2d[] address */ 782 ldx %r25, %r25, %r21 /* get pdir address, i.e. pmap->pm_pp2d[pp2d_idx] * */ 783 784 cmpdi %r25, 0 785 beq 2f 786 787 rldicl %r21, %r31, (64 - PDIR_L1_L), (64 - PDIR_L1_NUM) /* pp2d offset */ 788 slwi %r21, %r21, PDIR_L1_ENTRY_SHIFT /* multiply by pp2d entry size */ 789 ldx %r25, %r25, %r21 /* get pdir address, i.e. pmap->pm_pp2d[pp2d_idx] * */ 790 791 cmpdi %r25, 0 792 beq 2f 793 794 rldicl %r21, %r31, (64 - PDIR_L), (64 - PDIR_NUM) /* pdir offset */ 795 slwi %r21, %r21, PDIR_ENTRY_SHIFT /* multiply by pdir entry size */ 796 ldx %r25, %r25, %r21 /* get ptbl address, i.e. pmap->pm_pp2d[pp2d_idx][pdir_idx] */ 797 798 cmpdi %r25, 0 799 beq 2f 800 801 rldicl %r21, %r31, (64 - PTBL_L), (64 - PTBL_NUM) /* ptbl offset */ 802 slwi %r21, %r21, PTBL_ENTRY_SHIFT /* multiply by pte entry size */ 803 804#else 805 srwi %r21, %r31, PDIR_SHIFT /* pdir offset */ 806 slwi %r21, %r21, PDIR_ENTRY_SHIFT /* multiply by pdir entry size */ 807 808 lwz %r25, PM_PDIR(%r26) /* pmap pm_dir[] address */ 809 /* 810 * Get ptbl address, i.e. pmap->pm_pdir[pdir_idx] 811 * This load may cause a Data TLB miss for non-kernel pmap! 812 */ 813 lwzx %r25, %r25, %r21 /* offset within pm_pdir[] table */ 814 cmpwi %r25, 0 815 beq 2f 816 817 lis %r21, PTBL_MASK@h 818 ori %r21, %r21, PTBL_MASK@l 819 and %r21, %r21, %r31 820 821 /* ptbl offset, multiply by ptbl entry size */ 822 srwi %r21, %r21, (PTBL_SHIFT - PTBL_ENTRY_SHIFT) 823#endif 824 825 add %r25, %r25, %r21 /* address of pte entry */ 826 /* 827 * Get pte->flags 828 * This load may cause a Data TLB miss for non-kernel pmap! 829 */ 830 lwz %r21, PTE_FLAGS(%r25) 831 andi. %r21, %r21, PTE_VALID@l 832 bne 2f 8331: 834 li %r25, 0 8352: 836 blr 837 838/***************************************************************************** 839 * 840 * Load MAS1-MAS3 registers with data, write TLB entry 841 * 842 * input: 843 * r29 - mas0 844 * r28 - mas1 845 * r27 - mas2 846 * r25 - pte 847 * 848 * output: none 849 * 850 * scratch regs: r21-r23 851 * 852 ****************************************************************************/ 853tlb_fill_entry: 854 /* 855 * Update PTE flags: we have to do it atomically, as pmap_protect() 856 * running on other CPUs could attempt to update the flags at the same 857 * time. 858 */ 859 li %r23, PTE_FLAGS 8601: 861 lwarx %r21, %r23, %r25 /* get pte->flags */ 862 oris %r21, %r21, PTE_REFERENCED@h /* set referenced bit */ 863 864 andi. %r22, %r21, (PTE_SW | PTE_UW)@l /* check if writable */ 865 beq 2f 866 ori %r21, %r21, PTE_MODIFIED@l /* set modified bit */ 8672: 868 stwcx. %r21, %r23, %r25 /* write it back */ 869 bne- 1b 870 871 /* Update MAS2. */ 872 rlwimi %r27, %r21, 13, 27, 30 /* insert WIMG bits from pte */ 873 874 /* Setup MAS3 value in r23. */ 875 LOAD %r23, PTE_RPN(%r25) /* get pte->rpn */ 876#ifdef __powerpc64__ 877 rldicr %r22, %r23, 52, 51 /* extract MAS3 portion of RPN */ 878 rldicl %r23, %r23, 20, 54 /* extract MAS7 portion of RPN */ 879 880 rlwimi %r22, %r21, 30, 26, 31 /* insert protection bits from pte */ 881#else 882 rlwinm %r22, %r23, 20, 0, 11 /* extract MAS3 portion of RPN */ 883 884 rlwimi %r22, %r21, 30, 26, 31 /* insert protection bits from pte */ 885 rlwimi %r22, %r21, 20, 12, 19 /* insert lower 8 RPN bits to MAS3 */ 886 rlwinm %r23, %r23, 20, 24, 31 /* MAS7 portion of RPN */ 887#endif 888 889 /* Load MAS registers. */ 890 mtspr SPR_MAS0, %r29 891 mtspr SPR_MAS1, %r28 892 mtspr SPR_MAS2, %r27 893 mtspr SPR_MAS3, %r22 894 mtspr SPR_MAS7, %r23 895 896 isync 897 tlbwe 898 isync 899 msync 900 blr 901 902/***************************************************************************** 903 * Instruction TLB miss interrupt 904 * 905 * Same notes as for the Data TLB miss 906 ****************************************************************************/ 907INTERRUPT(int_inst_tlb_error) 908 TLB_PROLOG 909 TLB_LOCK 910 911 mfsrr0 %r31 /* faulting address */ 912 913 /* 914 * Save MAS0-MAS2 registers. There might be another tlb miss during pte 915 * lookup overwriting current contents (which was hw filled). 916 */ 917 mfspr %r29, SPR_MAS0 918 mfspr %r28, SPR_MAS1 919 mfspr %r27, SPR_MAS2 920 921 mfsrr1 %r21 922 mtcr %r21 923 924 /* check MSR[PR] */ 925 bt 17, search_user_pmap 926 b search_kernel_pmap 927 928 929 .globl interrupt_vector_top 930interrupt_vector_top: 931 932/***************************************************************************** 933 * Debug interrupt 934 ****************************************************************************/ 935INTERRUPT(int_debug) 936 STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_CSRR0, SPR_CSRR1) 937 FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG) 938 bl int_debug_int 939 FRAME_LEAVE(SPR_CSRR0, SPR_CSRR1) 940 rfci 941 942INTERRUPT(int_debug_ed) 943 STANDARD_CRIT_PROLOG(SPR_SPRG2, PC_BOOKE_CRITSAVE, SPR_DSRR0, SPR_DSRR1) 944 FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG) 945 bl int_debug_int 946 FRAME_LEAVE(SPR_DSRR0, SPR_DSRR1) 947 rfdi 948 /* .long 0x4c00004e */ 949 950/* Internal helper for debug interrupt handling. */ 951/* Common code between e500v1/v2 and e500mc-based cores. */ 952int_debug_int: 953 mflr %r14 954 GET_CPUINFO(%r3) 955 LOAD %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r3) 956 bl 0f 957 ADDR(interrupt_vector_base-.) 958 ADDR(interrupt_vector_top-.) 9590: mflr %r5 960 LOAD %r4,0(%r5) /* interrupt_vector_base in r4 */ 961 add %r4,%r4,%r5 962 CMPL cr0, %r3, %r4 963 blt trap_common 964 LOAD %r4,WORD_SIZE(%r5) /* interrupt_vector_top in r4 */ 965 add %r4,%r4,%r5 966 addi %r4,%r4,4 967 CMPL cr0, %r3, %r4 968 bge trap_common 969 /* Disable single-stepping for the interrupt handlers. */ 970 LOAD %r3, FRAME_SRR1+CALLSIZE(%r1); 971 rlwinm %r3, %r3, 0, 23, 21 972 STORE %r3, FRAME_SRR1+CALLSIZE(%r1); 973 /* Restore srr0 and srr1 as they could have been clobbered. */ 974 GET_CPUINFO(%r4) 975 LOAD %r3, (PC_BOOKE_CRITSAVE+BOOKE_CRITSAVE_SRR0)(%r4); 976 mtspr SPR_SRR0, %r3 977 LOAD %r4, (PC_BOOKE_CRITSAVE+BOOKE_CRITSAVE_SRR1)(%r4); 978 mtspr SPR_SRR1, %r4 979 mtlr %r14 980 blr 981 982/***************************************************************************** 983 * Common trap code 984 ****************************************************************************/ 985trap_common: 986 /* Call C trap dispatcher */ 987 GET_TOCBASE(%r2) 988 addi %r3, %r1, CALLSIZE 989 bl CNAME(powerpc_interrupt) 990 TOC_RESTORE 991 992 .globl CNAME(trapexit) /* exported for db_backtrace use */ 993CNAME(trapexit): 994 /* disable interrupts */ 995 wrteei 0 996 997 /* Test AST pending - makes sense for user process only */ 998 LOAD %r5, FRAME_SRR1+CALLSIZE(%r1) 999 mtcr %r5 1000 bf 17, 1f 1001 1002 GET_CPUINFO(%r3) 1003 LOAD %r4, PC_CURTHREAD(%r3) 1004 lwz %r4, TD_AST(%r4) 1005 cmpwi %r4, 0 1006 beq 1f 1007 1008 /* re-enable interrupts before calling ast() */ 1009 wrteei 1 1010 1011 addi %r3, %r1, CALLSIZE 1012 bl CNAME(ast) 1013 TOC_RESTORE 1014 .globl CNAME(asttrapexit) /* db_backtrace code sentinel #2 */ 1015CNAME(asttrapexit): 1016 b trapexit /* test ast ret value ? */ 10171: 1018 FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 1019 rfi 1020 1021 1022#if defined(KDB) 1023/* 1024 * Deliberate entry to dbtrap 1025 */ 1026 /* .globl CNAME(breakpoint)*/ 1027ASENTRY_NOPROF(breakpoint) 1028 mtsprg1 %r1 1029 mfmsr %r3 1030 mtsrr1 %r3 1031 li %r4, ~(PSL_EE | PSL_ME)@l 1032 oris %r4, %r4, ~(PSL_EE | PSL_ME)@h 1033 and %r3, %r3, %r4 1034 mtmsr %r3 /* disable interrupts */ 1035 isync 1036 GET_CPUINFO(%r3) 1037 STORE %r30, (PC_DBSAVE+CPUSAVE_R30)(%r3) 1038 STORE %r31, (PC_DBSAVE+CPUSAVE_R31)(%r3) 1039 1040 mflr %r31 1041 mtsrr0 %r31 1042 1043 mfspr %r30, SPR_DEAR 1044 mfspr %r31, SPR_ESR 1045 STORE %r30, (PC_DBSAVE+CPUSAVE_BOOKE_DEAR)(%r3) 1046 STORE %r31, (PC_DBSAVE+CPUSAVE_BOOKE_ESR)(%r3) 1047 1048 mfsrr0 %r30 1049 mfsrr1 %r31 1050 STORE %r30, (PC_DBSAVE+CPUSAVE_SRR0)(%r3) 1051 STORE %r31, (PC_DBSAVE+CPUSAVE_SRR1)(%r3) 1052 isync 1053 1054 mfcr %r30 1055 1056/* 1057 * Now the kdb trap catching code. 1058 */ 1059dbtrap: 1060 FRAME_SETUP(SPR_SPRG1, PC_DBSAVE, EXC_DEBUG) 1061/* Call C trap code: */ 1062 GET_TOCBASE(%r2) 1063 addi %r3, %r1, CALLSIZE 1064 bl CNAME(db_trap_glue) 1065 TOC_RESTORE 1066 or. %r3, %r3, %r3 1067 bne dbleave 1068/* This wasn't for KDB, so switch to real trap: */ 1069 b trap_common 1070 1071dbleave: 1072 FRAME_LEAVE(SPR_SRR0, SPR_SRR1) 1073 rfi 1074ASEND(breakpoint) 1075#endif /* KDB */ 1076 1077#ifdef SMP 1078ENTRY(tlb_lock) 1079 GET_CPUINFO(%r5) 1080 LOAD %r5, PC_CURTHREAD(%r5) 10811: LOADX %r4, 0, %r3 1082 CMPI %r4, TLB_UNLOCKED 1083 bne 1b 1084 STOREX %r5, 0, %r3 1085 bne- 1b 1086 isync 1087 msync 1088 blr 1089END(tlb_lock) 1090 1091ENTRY(tlb_unlock) 1092 isync 1093 msync 1094 li %r4, TLB_UNLOCKED 1095 STORE %r4, 0(%r3) 1096 isync 1097 msync 1098 blr 1099END(tlb_unlock) 1100 1101/* 1102 * TLB miss spin locks. For each CPU we have a reservation granule (32 bytes); 1103 * only a single word from this granule will actually be used as a spin lock 1104 * for mutual exclusion between TLB miss handler and pmap layer that 1105 * manipulates page table contents. 1106 */ 1107 .data 1108 .align 5 1109GLOBAL(tlb0_miss_locks) 1110 .space RES_GRANULE * MAXCPU 1111#endif 1112