| /src/contrib/arm-optimized-routines/math/aarch64/experimental/ |
| H A D | erfc_1u8.c | 26 #define Q6 0x1.2aaaaaaaaaaabp0 macro
108 double p7 = fma (Q6 * r, p6, p5) * R6; in erfc()
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| /src/lib/msun/bsdsrc/ |
| H A D | b_tgamma.c | 175 Q6 = -1.7601274143166700e-3, variable
186 z * (Q6 + z * (Q7 + z * Q8))))))); in ratfun_gam()
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| /src/lib/msun/ld80/ |
| H A D | b_tgammal.c | 198 #define Q6 (Q6u.e) macro
209 z * (Q6 + z * (Q7 + z * Q8))))))); in ratfun_gam()
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| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.cpp | 37 AArch64::Q6, AArch64::Q7};
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| H A D | AArch64PBQPRegAlloc.cpp | 124 case AArch64::Q6: in isOdd()
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| H A D | AArch64CallingConvention.td | 108 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
154 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
397 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
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| H A D | AArch64RegisterInfo.td | 424 def Q6 : AArch64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias<B6>;
864 def Z6 : AArch64Reg<6, "z6", [Q6]>, DwarfRegNum<[102]>;
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| H A D | AArch64FastISel.cpp | 2970 AArch64::Q5, AArch64::Q6, AArch64::Q7 } in fastLowerArguments()
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| /src/sys/contrib/device-tree/src/arm/allwinner/ |
| H A D | sun8i-v3s-netcube-kumquat.dts | 199 "I4", "I5", "Q5", "Q6",
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| /src/sys/contrib/device-tree/Bindings/net/wireless/ |
| H A D | qcom,ath10k.txt | 74 used by the wifi firmware running in Q6.
|
| /src/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 97 SP::Q6, SP::Q14, ~0U, ~0U,
|
| /src/sys/contrib/device-tree/src/arm/aspeed/ |
| H A D | aspeed-bmc-tyan-s8036.dts | 448 /*Q6*/ "id-button", /* in: BMC_CHASSIS_ID_BTN_L */
|
| H A D | aspeed-bmc-tyan-s7106.dts | 508 /*Q6*/ "",
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| /src/contrib/file/tests/ |
| H A D | HWP97.hwp.testfile | 32 …˧ď�tfR��j�������"��=c�Mx��˜X�{��%��6]�`q}l��M���QήD�1P�Z.0=Jp ���'��Q6�N�˩�M��� ]P gXwp5%{…
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCTargetDesc.cpp | 318 {codeview::RegisterId::ARM_NQ6, ARM::Q6}, in initLLVMToCVRegMapping()
|
| H A D | ARMMCCodeEmitter.cpp | 562 case ARM::Q4: case ARM::Q5: case ARM::Q6: case ARM::Q7: in getMachineOpValue()
|
| /src/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 211 {codeview::RegisterId::ARM64_Q6, AArch64::Q6}, in initLLVMToCVRegMapping()
|
| H A D | AArch64InstPrinter.cpp | 1517 case AArch64::Q5: Reg = AArch64::Q6; break; in getNextVectorRegister()
1518 case AArch64::Q6: Reg = AArch64::Q7; break; in getNextVectorRegister()
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| /src/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.td | 287 def Q6 : Rq<24, "f24", [D12, D13]>;
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| /src/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/ |
| H A D | VEDisassembler.cpp | 93 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
|
| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterInfo.td | 165 def Q6 : ARMReg< 6, "q6", [D12, D13]>;
|
| /src/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 181 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
|
| /src/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 126 VE::Q0, VE::Q1, VE::Q2, VE::Q3, VE::Q4, VE::Q5, VE::Q6, VE::Q7,
|
| /src/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1573 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1593 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
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| /src/contrib/ncurses/include/ |
| H A D | Caps.hpux11 | 833 enter_vertical_hl_mode evhlm str Q6 - - ----- Enter vertical highlight mode
|