Searched refs:PPR (Results 1 – 8 of 8) sorted by relevance
| /src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 1273 (!cast<Instruction>(Inst # _SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1276 (!cast<Instruction>(Inst # _SXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1279 (!cast<Instruction>(Inst # _UXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1285 (!cast<Instruction>(Inst # _IMM) PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>; 1288 (!cast<Instruction>(Inst) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1291 (!cast<Instruction>(Inst # _SXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1294 (!cast<Instruction>(Inst # _UXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>; 1299 (Inst PPR:$gp, GPR64:$base, ZPR:$offs)>; 1507 (!cast<Instruction>(Inst # _SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; 1510 (!cast<Instruction>(Inst # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; [all …]
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| H A D | AArch64RegisterInfo.td | 930 def PPR : PPRClass<0, 15> { 949 def PPRAsmOpAny : PPRAsmOperand<"PredicateAny", "PPR", 0>; 950 def PPRAsmOp8 : PPRAsmOperand<"PredicateB", "PPR", 8>; 951 def PPRAsmOp16 : PPRAsmOperand<"PredicateH", "PPR", 16>; 952 def PPRAsmOp32 : PPRAsmOperand<"PredicateS", "PPR", 32>; 953 def PPRAsmOp64 : PPRAsmOperand<"PredicateD", "PPR", 64>; 959 def PPRAny : PPRRegOp<"", PPRAsmOpAny, ElementSizeNone, PPR>; 960 def PPR8 : PPRRegOp<"b", PPRAsmOp8, ElementSizeB, PPR>; 961 def PPR16 : PPRRegOp<"h", PPRAsmOp16, ElementSizeH, PPR>; 962 def PPR32 : PPRRegOp<"s", PPRAsmOp32, ElementSizeS, PPR>; [all …]
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| H A D | AArch64FrameLowering.cpp | 2917 enum RegType { GPR, FPR64, FPR128, PPR, ZPR, VG } Type; enumerator 2925 case PPR: in getScale() 2938 bool isScalable() const { return Type == PPR || Type == ZPR; } in isScalable() 2995 RPI.Type = RegPairInfo::PPR; in computeCalleeSaveRegisterPairs() 3030 case RegPairInfo::PPR: in computeCalleeSaveRegisterPairs() 3222 case RegPairInfo::PPR: in spillCalleeSavedRegisters() 3318 return c.Reg1 == RegPairInfo::PPR; in spillCalleeSavedRegisters() 3377 if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) { in spillCalleeSavedRegisters() 3417 auto IsPPR = [](const RegPairInfo &c) { return c.Type == RegPairInfo::PPR; }; in restoreCalleeSavedRegisters() 3463 case RegPairInfo::PPR: in restoreCalleeSavedRegisters() [all …]
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| H A D | SVEInstrFormats.td | 6503 …def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), v… 6504 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6505 …def : Pat<(sxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), v… 6506 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6523 …def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v… 6524 … (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6525 …def : Pat<(sxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v… 6526 … (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; 6543 …def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), v… 6544 (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>; [all …]
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| /src/sys/dev/aic7xxx/ |
| H A D | aic79xx.reg | 2482 * Data Transfer Negotiation Data - PPR Options
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| H A D | aic79xx.seq | 569 * agreement. Since SPI4 only allows target reset or PPR
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| /src/contrib/one-true-awk/testdir/ |
| H A D | funstack.in | 5588 @Article{Lesk:1972:PPR,
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| /src/contrib/ncurses/misc/ |
| H A D | terminfo.src | 24879 # PPR Page Position Forward * \E [ Pn SPC Q 1 FE -
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