| /src/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineShifts.cpp | 147 BinaryOperator *NewShift = BinaryOperator::Create(ShiftOpcode, X, NewShAmt); in reassociateShiftAmtsOfTwoSameDirectionShifts() local
154 NewShift->setHasNoUnsignedWrap(Sh0->hasNoUnsignedWrap() && in reassociateShiftAmtsOfTwoSameDirectionShifts()
156 NewShift->setHasNoSignedWrap(Sh0->hasNoSignedWrap() && in reassociateShiftAmtsOfTwoSameDirectionShifts()
159 NewShift->setIsExact(Sh0->isExact() && Sh1->isExact()); in reassociateShiftAmtsOfTwoSameDirectionShifts()
163 Instruction *Ret = NewShift; in reassociateShiftAmtsOfTwoSameDirectionShifts()
165 Builder.Insert(NewShift); in reassociateShiftAmtsOfTwoSameDirectionShifts()
166 Ret = CastInst::Create(Instruction::Trunc, NewShift, Sh0->getType()); in reassociateShiftAmtsOfTwoSameDirectionShifts()
334 auto *NewShift = BinaryOperator::Create(OuterShift->getOpcode(), X, in dropRedundantMaskingOfLeftShiftInput() local
337 return NewShift; in dropRedundantMaskingOfLeftShiftInput()
339 Builder.Insert(NewShift); in dropRedundantMaskingOfLeftShiftInput()
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| H A D | InstCombineCompares.cpp | 1730 Value *NewShift = in foldICmpAndShift() local
1735 Value *NewAnd = Builder.CreateAnd(Shift->getOperand(0), NewShift); in foldICmpAndShift()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4049 SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt); in performShlCombine() local
4053 SDValue Vec = DAG.getBuildVector(MVT::v2i32, SL, {Zero, NewShift}); in performShlCombine()
4073 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
4076 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {Hi, NewShift}); in performSraCombine()
4083 SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi, in performSraCombine() local
4085 SDValue BuildVec = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, NewShift}); in performSraCombine()
4133 SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst); in performSrlCombine() local
4135 SDValue BuildPair = DAG.getBuildVector(MVT::v2i32, SL, {NewShift, Zero}); in performSrlCombine()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2135 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1)); in foldMaskedShiftToScaledMask() local
2144 insertDAGNode(DAG, N, NewShift); in foldMaskedShiftToScaledMask()
2145 DAG.ReplaceAllUsesWith(N, NewShift); in foldMaskedShiftToScaledMask()
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| H A D | X86ISelLowering.cpp | 42761 SDValue NewShift = TLO.DAG.getNode( in SimplifyDemandedBitsForTargetNode() local
42764 return TLO.CombineTo(Op, NewShift); in SimplifyDemandedBitsForTargetNode()
48307 SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1); in combineShiftRightLogical() local
48308 return DAG.getNode(ISD::AND, DL, VT, NewShift, NewMask); in combineShiftRightLogical()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2709 Register NewShift = in applyCombineTruncOfShift() local
2715 replaceRegWith(MRI, Dst, NewShift); in applyCombineTruncOfShift()
2717 Builder.buildTrunc(Dst, NewShift); in applyCombineTruncOfShift()
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| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2618 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT, in foldAddSubOfSignBit() local
2620 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC); in foldAddSubOfSignBit()
6898 SDValue NewShift = DAG.getNode(ShiftOpcode, DL, VT, LogicX, Y); in foldLogicOfShifts() local
6899 return DAG.getNode(LogicOpcode, DL, VT, NewShift, Z); in foldLogicOfShifts()
9750 SDValue NewShift = DAG.getNode(N->getOpcode(), DL, VT, LHS.getOperand(0), in visitShiftByConstant() local
9752 return DAG.getNode(LHS.getOpcode(), DL, VT, NewShift, NewRHS); in visitShiftByConstant()
10589 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
10591 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewShift); in visitSRL()
10598 SDValue NewShift = DAG.getNode(ISD::SRL, DL, InnerShiftVT, in visitSRL() local
10603 SDValue And = DAG.getNode(ISD::AND, DL, InnerShiftVT, NewShift, Mask); in visitSRL()
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| H A D | TargetLowering.cpp | 1885 SDValue NewShift = TLO.DAG.getNode(ISD::SHL, dl, HalfVT, NewOp, in SimplifyDemandedBits() local
1888 TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift); in SimplifyDemandedBits()
1982 SDValue NewShift = in SimplifyDemandedBits() local
1985 Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, VT, NewShift)); in SimplifyDemandedBits()
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| /src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 17483 SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1, in PerformLongShiftCombine() local
17485 DAG.ReplaceAllUsesWith(N, NewShift.getNode()); in PerformLongShiftCombine()
17486 return NewShift; in PerformLongShiftCombine()
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