Searched refs:MidRegLo (Results 1 – 1 of 1) sorted by relevance
8174 Register MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local8178 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32_e64), MidRegLo) in splitScalar64BitBFE()8185 .addReg(MidRegLo); in splitScalar64BitBFE()8188 .addReg(MidRegLo) in splitScalar64BitBFE()