| /src/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1366 SDValue MaskLo, MaskHi; in SplitMask() local
1369 GetSplitVector(Mask, MaskLo, MaskHi); in SplitMask()
1371 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL); in SplitMask()
1372 return std::make_pair(MaskLo, MaskHi); in SplitMask()
1393 SDValue MaskLo, MaskHi; in SplitVecRes_BinOp() local
1394 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(2)); in SplitVecRes_BinOp()
1403 {LHSHi, RHSHi, MaskHi, EVLHi}, Flags); in SplitVecRes_BinOp()
1427 SDValue MaskLo, MaskHi; in SplitVecRes_TernaryOp() local
1428 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(3)); in SplitVecRes_TernaryOp()
1437 {Op0Hi, Op1Hi, Op2Hi, MaskHi, EVLHi}, Flags); in SplitVecRes_TernaryOp()
[all …]
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| H A D | LegalizeIntegerTypes.cpp | 1666 SDValue MaskLo, MaskHi, EVLLo, EVLHi; in PromoteIntRes_TRUNCATE() local
1667 std::tie(MaskLo, MaskHi) = SplitMask(N->getOperand(1)); in PromoteIntRes_TRUNCATE()
1671 EOp2 = DAG.getNode(ISD::VP_TRUNCATE, dl, HalfNVT, EOp2, MaskHi, EVLHi); in PromoteIntRes_TRUNCATE()
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| H A D | TargetLowering.cpp | 2406 APInt MaskHi = DemandedBits.getHiBits(HalfBitWidth).trunc(HalfBitWidth); in SimplifyDemandedBits() local
2413 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownHi, TLO, Depth + 1)) in SimplifyDemandedBits()
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| /src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 2989 Register MaskHi = MRI->createVirtualRegister(&RegRC); in selectG_PTRMASK() local
2992 BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), MaskHi) in selectG_PTRMASK()
2996 .addReg(MaskHi); in selectG_PTRMASK()
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| /src/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 23588 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
23589 SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
23599 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
23600 SDValue Result = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
23638 static const int MaskHi[] = { 1, 1, 3, 3 }; in LowerVSETCC() local
23640 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi); in LowerVSETCC()
23642 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi); in LowerVSETCC()
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| /src/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6197 auto [MaskLo, MaskHi] = DAG.SplitVector(Op.getOperand(2), DL); in SplitVectorReductionOp()
6205 {ResLo, Hi, MaskHi, EVLHi}, Op->getFlags()); in SplitVectorReductionOp()
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