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Searched refs:MVT (Results 1 – 25 of 285) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp268 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty); in getArithmeticInstrCost()
274 (LT.second.getScalarType() == MVT::i32 || in getArithmeticInstrCost()
275 LT.second.getScalarType() == MVT::i64)) { in getArithmeticInstrCost()
287 LT.second.getScalarType() == MVT::i32) { in getArithmeticInstrCost()
302 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); in getArithmeticInstrCost()
308 if (ST->useSLMArithCosts() && LT.second == MVT::v4i32) { in getArithmeticInstrCost()
322 if (!SignedMode && OpMinSize <= 32 && LT.second.getScalarType() == MVT::i64) in getArithmeticInstrCost()
375 { ISD::SHL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
376 { ISD::SRL, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
377 { ISD::SRA, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
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H A DX86ISelLowering.cpp131 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); in X86TargetLowering()
142 setOperationAction(ISD::CLEAR_CACHE, MVT::Other, Expand); in X86TargetLowering()
196 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
197 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
198 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
200 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
202 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering()
203 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
206 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
207 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
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/src/contrib/llvm-project/llvm/include/llvm/CodeGenTypes/
H A DMachineValueType.h34 class MVT {
55 constexpr MVT() = default;
56 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() function
58 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
59 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
60 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
61 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
62 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
63 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
73 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp494 return (EltVT == MVT::f32 && ST->hasVFP2Base()) || in getCastInstrCost()
495 (EltVT == MVT::f64 && ST->hasFP64()) || in getCastInstrCost()
496 (EltVT == MVT::f16 && ST->hasFullFP16()); in getCastInstrCost()
523 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
524 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
525 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
526 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
527 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
528 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
529 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
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H A DARMCallingConv.h20 bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
23 bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
26 bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
29 bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
32 bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
35 bool CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
38 bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
41 bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
44 bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
47 bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp145 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64); in SelectAddrModeIndexedUImm()
202 Res2 = CurDAG->getTargetConstant(ShtAmt, SDLoc(N), MVT::i32); in SelectRoundingVLShr()
254 template<MVT::SimpleValueType VT>
259 template <MVT::SimpleValueType VT, bool Negate>
264 template <MVT::SimpleValueType VT>
269 template <MVT::SimpleValueType VT, bool Invert = false>
274 template <MVT::SimpleValueType VT>
309 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectCntImm()
325 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectEXTImm()
340 Imm = CurDAG->getRegister(BaseReg + C, MVT::Other); in ImmToReg()
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H A DAArch64TargetTransformInfo.cpp562 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
563 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
564 MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, in getIntrinsicInstrCost()
565 MVT::nxv2i64}; in getIntrinsicInstrCost()
568 if (LT.second == MVT::v2i64) in getIntrinsicInstrCost()
570 if (any_of(ValidMinMaxTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
578 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
579 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
580 MVT::v2i64}; in getIntrinsicInstrCost()
586 if (any_of(ValidSatTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
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H A DAArch64CallingConvention.h19 bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
22 bool CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool CC_AArch64_Arm64EC_Thunk(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool CC_AArch64_Arm64EC_Thunk_Native(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
46 bool CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
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H A DAArch64FastISel.cpp185 bool isTypeLegal(Type *Ty, MVT &VT);
186 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
190 bool simplifyAddress(Address &Addr, MVT VT);
199 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
204 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
207 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
213 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
217 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
225 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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/src/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp110 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
111 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
112 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
113 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
114 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
121 if (OpVT == MVT::f16) { in getFPEXT()
122 if (RetVT == MVT::f32) in getFPEXT()
124 if (RetVT == MVT::f64) in getFPEXT()
126 if (RetVT == MVT::f80) in getFPEXT()
128 if (RetVT == MVT::f128) in getFPEXT()
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H A DValueTypes.cpp173 case MVT::bf16: return "bf16"; in getEVTString()
174 case MVT::ppcf128: return "ppcf128"; in getEVTString()
175 case MVT::isVoid: return "isVoid"; in getEVTString()
176 case MVT::Other: return "ch"; in getEVTString()
177 case MVT::Glue: return "glue"; in getEVTString()
178 case MVT::x86mmx: return "x86mmx"; in getEVTString()
179 case MVT::x86amx: return "x86amx"; in getEVTString()
180 case MVT::i64x8: return "i64x8"; in getEVTString()
181 case MVT::Metadata: return "Metadata"; in getEVTString()
182 case MVT::Untyped: return "Untyped"; in getEVTString()
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/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp23 MVT WebAssembly::parseMVT(StringRef Type) { in parseMVT()
24 return StringSwitch<MVT>(Type) in parseMVT()
25 .Case("i32", MVT::i32) in parseMVT()
26 .Case("i64", MVT::i64) in parseMVT()
27 .Case("f32", MVT::f32) in parseMVT()
28 .Case("f64", MVT::f64) in parseMVT()
29 .Case("i64", MVT::i64) in parseMVT()
30 .Case("v16i8", MVT::v16i8) in parseMVT()
31 .Case("v8i16", MVT::v8i16) in parseMVT()
32 .Case("v4i32", MVT::v4i32) in parseMVT()
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/src/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp84 return TII->ExpandMOVI(MIB, MVT::i8); in INITIALIZE_PASS()
86 return TII->ExpandMOVI(MIB, MVT::i16); in INITIALIZE_PASS()
88 return TII->ExpandMOVI(MIB, MVT::i32); in INITIALIZE_PASS()
91 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in INITIALIZE_PASS()
93 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in INITIALIZE_PASS()
95 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in INITIALIZE_PASS()
98 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in INITIALIZE_PASS()
100 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in INITIALIZE_PASS()
102 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in INITIALIZE_PASS()
105 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in INITIALIZE_PASS()
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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp46 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
75 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
76 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
78 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
79 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
81 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
82 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
84 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
85 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
87 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
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H A DSIISelLowering.cpp88 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
89 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
91 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
92 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
94 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
99 addRegisterClass(MVT::f64, V64RegClass); in SITargetLowering()
100 addRegisterClass(MVT::v2f32, V64RegClass); in SITargetLowering()
101 addRegisterClass(MVT::Untyped, V64RegClass); in SITargetLowering()
103 addRegisterClass(MVT::v3i32, &AMDGPU::SGPR_96RegClass); in SITargetLowering()
104 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
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H A DR600ISelLowering.cpp33 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
46 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
51 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
52 setLoadExtAction(Op, VT, MVT::i1, Promote); in R600TargetLowering()
53 setLoadExtAction(Op, VT, MVT::i8, Custom); in R600TargetLowering()
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/src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp34 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
35 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
36 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
37 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
39 static std::tuple<unsigned, unsigned, unsigned> getIEEEProperties(MVT Ty) { in getIEEEProperties()
41 MVT ElemTy = Ty.getScalarType(); in getIEEEProperties()
43 case MVT::f16: in getIEEEProperties()
45 case MVT::f32: in getIEEEProperties()
47 case MVT::f64: in getIEEEProperties()
58 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
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H A DHexagonISelLowering.cpp140 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
177 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
260 return DAG.getNode(HexagonISD::RET_GLUE, dl, MVT::Other, RetOps); in LowerReturn()
368 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
376 MVT::i32, Glue); in LowerCallResult()
385 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
423 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); in LowerCall()
500 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
533 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
583 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
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/src/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp44 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
45 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
57 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
58 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
83 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
84 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
107 static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, in Analyze_CC_Sparc64_Full()
108 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in Analyze_CC_Sparc64_Full()
110 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in Analyze_CC_Sparc64_Full()
115 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in Analyze_CC_Sparc64_Full()
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/src/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp119 MVT::SimpleValueType getSimpleType(Type *Ty) { in getSimpleType()
122 : MVT::INVALID_SIMPLE_VALUE_TYPE; in getSimpleType()
124 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) { in getLegalType()
126 case MVT::i1: in getLegalType()
127 case MVT::i8: in getLegalType()
128 case MVT::i16: in getLegalType()
129 return MVT::i32; in getLegalType()
130 case MVT::i32: in getLegalType()
131 case MVT::i64: in getLegalType()
132 case MVT::f32: in getLegalType()
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H A DWebAssemblyISelLowering.cpp49 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
61 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
63 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
64 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
67 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
68 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
69 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
70 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp183 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
186 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
189 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
191 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
192 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
197 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
198 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
201 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
204 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in PPCTargetLowering()
205 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in PPCTargetLowering()
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H A DPPCFastISel.cpp111 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
140 bool isTypeLegal(Type *Ty, MVT &VT);
141 bool isLoadTypeLegal(Type *Ty, MVT &VT);
160 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
163 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
167 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
169 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
170 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
171 unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
177 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
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H A DPPCCallingConv.h22 bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_PPC64_ELF(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
/src/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp130 static bool IsPTXVectorType(MVT VT) { in IsPTXVectorType()
134 case MVT::v2i1: in IsPTXVectorType()
135 case MVT::v4i1: in IsPTXVectorType()
136 case MVT::v2i8: in IsPTXVectorType()
137 case MVT::v4i8: in IsPTXVectorType()
138 case MVT::v2i16: in IsPTXVectorType()
139 case MVT::v4i16: in IsPTXVectorType()
140 case MVT::v8i16: // <4 x i16x2> in IsPTXVectorType()
141 case MVT::v2i32: in IsPTXVectorType()
142 case MVT::v4i32: in IsPTXVectorType()
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