1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #ifndef __MT7996_H
7 #define __MT7996_H
8
9 #include <linux/interrupt.h>
10 #include <linux/ktime.h>
11 #if defined(__FreeBSD__)
12 #include <linux/uuid.h>
13 #endif
14 #include "../mt76_connac.h"
15 #include "regs.h"
16
17 #define MT7996_MAX_RADIOS 3
18 #define MT7996_MAX_INTERFACES 19 /* per-band */
19 #define MT7996_MAX_WMM_SETS 4
20 #define MT7996_WTBL_BMC_SIZE (is_mt7996(&dev->mt76) ? 64 : 32)
21 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)
22 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \
23 mt7996_max_interface_num(dev))
24
25 #define MT7996_WATCHDOG_TIME (HZ / 10)
26 #define MT7996_RESET_TIMEOUT (30 * HZ)
27
28 #define MT7996_TX_RING_SIZE 2048
29 #define MT7996_TX_MCU_RING_SIZE 256
30 #define MT7996_TX_FWDL_RING_SIZE 128
31
32 #define MT7996_RX_RING_SIZE 1536
33 #define MT7996_RX_MCU_RING_SIZE 512
34 #define MT7996_RX_MCU_RING_SIZE_WA 1024
35 /* scatter-gather of mcu event is not supported in connac3 */
36 #define MT7996_RX_MCU_BUF_SIZE (2048 + \
37 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
38
39 #define MT7996_DEVICE_ID 0x7990
40 #define MT7996_DEVICE_ID_2 0x7991
41 #define MT7992_DEVICE_ID 0x7992
42 #define MT7992_DEVICE_ID_2 0x799a
43 #define MT7990_DEVICE_ID 0x7993
44 #define MT7990_DEVICE_ID_2 0x799b
45
46 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"
47 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"
48 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin"
49 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"
50
51 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin"
52 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin"
53 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP
54 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin"
55
56 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin"
57 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin"
58 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin"
59 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin"
60
61 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin"
62 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin"
63 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin"
64 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin"
65
66 #define MT7990_FIRMWARE_WA ""
67 #define MT7990_FIRMWARE_WM "mediatek/mt7996/mt7990_wm.bin"
68 #define MT7990_FIRMWARE_DSP ""
69 #define MT7990_ROM_PATCH "mediatek/mt7996/mt7990_rom_patch.bin"
70
71 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"
72 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin"
73 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin"
74 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin"
75
76 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin"
77 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin"
78 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin"
79 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin"
80 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin"
81
82 #define MT7990_EEPROM_DEFAULT "mediatek/mt7996/mt7990_eeprom.bin"
83 #define MT7990_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7990_eeprom_2i5i.bin"
84
85 #define MT7996_EEPROM_SIZE 7680
86 #define MT7996_EEPROM_BLOCK_SIZE 16
87 #define MT7996_TOKEN_SIZE 16384
88 #define MT7996_HW_TOKEN_SIZE 8192
89
90 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
91 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
92 #define MT7996_IBF_MAX_NC 2
93 #define MT7996_IBF_TIMEOUT 0x18
94 #define MT7996_IBF_TIMEOUT_LEGACY 0x48
95
96 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */
97 #define MT7992_IBF_TIMEOUT 0xff
98
99 #define MT7996_SKU_RATE_NUM 417
100 #define MT7996_SKU_PATH_NUM 494
101
102 #define MT7996_MAX_TWT_AGRT 16
103 #define MT7996_MAX_STA_TWT_AGRT 8
104 #define MT7996_MIN_TWT_DUR 64
105 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)
106
107 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */
108 #define MT7996_BASIC_RATES_TBL 31
109 #define MT7996_BEACON_RATES_TBL 25
110
111 #define MT7996_THERMAL_THROTTLE_MAX 100
112 #define MT7996_CDEV_THROTTLE_MAX 99
113 #define MT7996_CRIT_TEMP_IDX 0
114 #define MT7996_MAX_TEMP_IDX 1
115 #define MT7996_CRIT_TEMP 110
116 #define MT7996_MAX_TEMP 120
117
118 #define MT7996_MAX_HIF_RXD_IN_PG 5
119 #define MT7996_RRO_MSDU_PG_HASH_SIZE 127
120 #define MT7996_RRO_MAX_SESSION 1024
121 #define MT7996_RRO_WINDOW_MAX_LEN 1024
122 #define MT7996_RRO_ADDR_ELEM_LEN 128
123 #define MT7996_RRO_BA_BITMAP_LEN 2
124 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \
125 MT7996_RRO_BA_BITMAP_LEN)
126 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \
127 MT7996_RRO_ADDR_ELEM_LEN)
128 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \
129 MT7996_RRO_BA_BITMAP_SESSION_SIZE)
130
131 #define MT7996_RX_BUF_SIZE (1800 + \
132 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
133 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \
134 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
135
136 /* RRO 3.1 */
137 #define MT7996_RRO_MSDU_PG_CR_CNT 8
138 #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000
139
140 struct mt7996_vif;
141 struct mt7996_sta;
142 struct mt7996_dfs_pulse;
143 struct mt7996_dfs_pattern;
144
145 enum mt7996_ram_type {
146 MT7996_RAM_TYPE_WM,
147 MT7996_RAM_TYPE_WA,
148 MT7996_RAM_TYPE_DSP,
149 };
150
151 enum mt7996_var_type {
152 MT7996_VAR_TYPE_444,
153 MT7996_VAR_TYPE_233,
154 };
155
156 enum mt7992_var_type {
157 MT7992_VAR_TYPE_44,
158 MT7992_VAR_TYPE_23,
159 };
160
161 enum mt7990_var_type {
162 MT7990_VAR_TYPE_23,
163 };
164
165 enum mt7996_fem_type {
166 MT7996_FEM_EXT,
167 MT7996_FEM_INT,
168 MT7996_FEM_MIX,
169 };
170
171 enum mt7996_txq_id {
172 MT7996_TXQ_FWDL = 16,
173 MT7996_TXQ_MCU_WM,
174 MT7996_TXQ_BAND0,
175 MT7996_TXQ_BAND1,
176 MT7996_TXQ_MCU_WA,
177 MT7996_TXQ_BAND2,
178 };
179
180 enum mt7996_rxq_id {
181 MT7996_RXQ_MCU_WM = 0,
182 MT7996_RXQ_MCU_WA,
183 MT7996_RXQ_MCU_WA_MAIN = 2,
184 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */
185 MT7996_RXQ_MCU_WA_TRI = 3,
186 MT7996_RXQ_BAND0 = 4,
187 MT7996_RXQ_BAND1 = 5, /* for mt7992 */
188 MT7996_RXQ_BAND2 = 5,
189 MT7996_RXQ_RRO_BAND0 = 8,
190 MT7996_RXQ_RRO_BAND1 = 9,
191 MT7996_RXQ_RRO_BAND2 = 6,
192 MT7996_RXQ_MSDU_PG_BAND0 = 10,
193 MT7996_RXQ_MSDU_PG_BAND1 = 11,
194 MT7996_RXQ_MSDU_PG_BAND2 = 12,
195 MT7996_RXQ_TXFREE0 = 9,
196 MT7996_RXQ_TXFREE1 = 9,
197 MT7996_RXQ_TXFREE2 = 7,
198 MT7996_RXQ_RRO_IND = 0,
199 MT7996_RXQ_RRO_RXDMAD_C = 0,
200 MT7990_RXQ_TXFREE0 = 6,
201 MT7990_RXQ_TXFREE1 = 7,
202 };
203
204 struct mt7996_twt_flow {
205 struct list_head list;
206 u64 start_tsf;
207 u64 tsf;
208 u32 duration;
209 u16 wcid;
210 __le16 mantissa;
211 u8 exp;
212 u8 table_id;
213 u8 id;
214 u8 protection:1;
215 u8 flowtype:1;
216 u8 trigger:1;
217 u8 sched:1;
218 };
219
220 DECLARE_EWMA(avg_signal, 10, 8)
221
222 struct mt7996_sta_link {
223 struct mt76_wcid wcid; /* must be first */
224
225 struct mt7996_sta *sta;
226
227 struct list_head rc_list;
228 u32 airtime_ac[8];
229
230 int ack_signal;
231 struct ewma_avg_signal avg_ack_signal;
232
233 unsigned long changed;
234
235 struct mt76_connac_sta_key_conf bip;
236
237 struct {
238 u8 flowid_mask;
239 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];
240 } twt;
241
242 struct rcu_head rcu_head;
243 };
244
245 struct mt7996_sta {
246 struct mt7996_sta_link deflink; /* must be first */
247 struct mt7996_sta_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
248 u8 deflink_id;
249 u8 seclink_id;
250
251 struct mt7996_vif *vif;
252 };
253
254 struct mt7996_vif_link {
255 struct mt76_vif_link mt76; /* must be first */
256
257 struct mt7996_sta_link msta_link;
258 struct mt7996_phy *phy;
259
260 struct cfg80211_bitrate_mask bitrate_mask;
261
262 u8 mld_idx;
263 };
264
265 struct mt7996_vif_link_info {
266 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
267 };
268
269 struct mt7996_vif {
270 struct mt7996_vif_link deflink; /* must be first */
271 struct mt76_vif_data mt76;
272
273 struct mt7996_vif_link_info link_info[IEEE80211_MLD_MAX_NUM_LINKS];
274
275 u8 mld_group_idx;
276 u8 mld_remap_idx;
277 };
278
279 /* crash-dump */
280 struct mt7996_crash_data {
281 guid_t guid;
282 struct timespec64 timestamp;
283
284 u8 *memdump_buf;
285 size_t memdump_buf_len;
286 };
287
288 struct mt7996_hif {
289 struct list_head list;
290
291 struct device *dev;
292 void __iomem *regs;
293 int irq;
294
295 enum pci_bus_speed speed;
296 enum pcie_link_width width;
297 };
298
299 #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24)
300 #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4)
301 #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0)
302 struct mt7996_wed_rro_addr {
303 __le32 head_low;
304 __le32 data;
305 };
306
307 struct mt7996_wed_rro_session_id {
308 struct list_head list;
309 u16 id;
310 };
311
312 struct mt7996_msdu_page {
313 struct list_head list;
314
315 struct mt76_queue *q;
316 dma_addr_t dma_addr;
317 void *buf;
318 };
319
320 /* data1 */
321 #define RRO_HIF_DATA1_LS_MASK BIT(30)
322 #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16)
323 /* data4 */
324 #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0)
325 struct mt7996_rro_hif {
326 __le32 data0;
327 __le32 data1;
328 __le32 data2;
329 __le32 data3;
330 __le32 data4;
331 __le32 data5;
332 };
333
334 #define MSDU_PAGE_INFO_OWNER_MASK BIT(31)
335 #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0)
336 struct mt7996_msdu_page_info {
337 struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG];
338 __le32 pg_low;
339 __le32 data;
340 };
341
342 #define MT7996_MAX_RRO_RRS_RING 4
343 struct mt7996_rro_queue_regs_emi {
344 struct {
345 __le16 idx;
346 __le16 rsv;
347 } ring[MT7996_MAX_RRO_RRS_RING];
348 };
349
350 struct mt7996_phy {
351 struct mt76_phy *mt76;
352 struct mt7996_dev *dev;
353
354 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
355
356 struct thermal_cooling_device *cdev;
357 u8 cdev_state;
358 u8 throttle_state;
359 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
360
361 u32 rxfilter;
362 u64 omac_mask;
363
364 u16 noise;
365
366 s16 coverage_class;
367 u8 slottime;
368
369 u16 beacon_rate;
370
371 u32 rx_ampdu_ts;
372 u32 ampdu_ref;
373 int txpower;
374
375 struct mt76_mib_stats mib;
376 struct mt76_channel_state state_ts;
377
378 u16 orig_chainmask;
379 u16 orig_antenna_mask;
380
381 bool has_aux_rx;
382 bool counter_reset;
383 };
384
385 struct mt7996_dev {
386 union { /* must be first */
387 struct mt76_dev mt76;
388 struct mt76_phy mphy;
389 };
390
391 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS];
392 struct wiphy_radio radios[MT7996_MAX_RADIOS];
393 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS];
394
395 struct mt7996_hif *hif2;
396 struct mt7996_reg_desc reg;
397 u8 q_id[MT7996_MAX_QUEUE];
398 u32 q_int_mask[MT7996_MAX_QUEUE];
399 u32 q_wfdma_mask;
400
401 u64 mld_idx_mask;
402 u64 mld_remap_idx_mask;
403
404 const struct mt76_bus_ops *bus_ops;
405 struct mt7996_phy phy;
406
407 /* monitor rx chain configured channel */
408 struct cfg80211_chan_def rdd2_chandef;
409 struct mt7996_phy *rdd2_phy;
410
411 u16 chainmask;
412 u8 chainshift[__MT_MAX_BAND];
413 u32 hif_idx;
414
415 struct work_struct init_work;
416 struct work_struct rc_work;
417 struct work_struct dump_work;
418 struct work_struct reset_work;
419 wait_queue_head_t reset_wait;
420 struct {
421 u32 state;
422 u32 wa_reset_count;
423 u32 wm_reset_count;
424 bool hw_full_reset:1;
425 bool hw_init_done:1;
426 bool restart:1;
427 } recovery;
428
429 /* protects coredump data */
430 struct mutex dump_mutex;
431 #ifdef CONFIG_DEV_COREDUMP
432 struct {
433 struct mt7996_crash_data *crash_data;
434 } coredump;
435 #endif
436
437 struct list_head sta_rc_list;
438 struct list_head twt_list;
439
440 u32 hw_pattern;
441
442 bool flash_mode:1;
443 bool has_eht:1;
444
445 struct {
446 struct {
447 void *ptr;
448 dma_addr_t phy_addr;
449 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN];
450 struct {
451 void *ptr;
452 dma_addr_t phy_addr;
453 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN];
454 struct {
455 void *ptr;
456 dma_addr_t phy_addr;
457 } session;
458 struct {
459 void *ptr;
460 dma_addr_t phy_addr;
461 } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT];
462 struct {
463 struct mt7996_rro_queue_regs_emi *ptr;
464 dma_addr_t phy_addr;
465 } emi_rings_cpu;
466 struct {
467 struct mt7996_rro_queue_regs_emi *ptr;
468 dma_addr_t phy_addr;
469 } emi_rings_dma;
470
471 struct work_struct work;
472 struct list_head poll_list;
473 spinlock_t lock;
474
475 struct list_head page_cache;
476 struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE];
477 } wed_rro;
478
479 bool ibf;
480 u8 fw_debug_wm;
481 u8 fw_debug_wa;
482 u8 fw_debug_bin;
483 u16 fw_debug_seq;
484
485 struct dentry *debugfs_dir;
486 struct rchan *relay_fwlog;
487
488 struct {
489 u16 table_mask;
490 u8 n_agrt;
491 } twt;
492
493 spinlock_t reg_lock;
494
495 u8 wtbl_size_group;
496 struct {
497 u8 type:4;
498 u8 fem:4;
499 } var;
500 };
501
502 enum {
503 WFDMA0 = 0x0,
504 WFDMA1,
505 WFDMA_EXT,
506 __MT_WFDMA_MAX,
507 };
508
509 enum rdd_idx {
510 MT_RDD_IDX_BAND2, /* RDD idx for band idx 2 */
511 MT_RDD_IDX_BAND1, /* RDD idx for band idx 1 */
512 MT_RDD_IDX_BACKGROUND, /* RDD idx for background chain */
513 };
514
515 enum mt7996_rdd_cmd {
516 RDD_STOP,
517 RDD_START,
518 RDD_DET_MODE,
519 RDD_RADAR_EMULATE,
520 RDD_START_TXQ = 20,
521 RDD_CAC_START = 50,
522 RDD_CAC_END,
523 RDD_NORMAL_START,
524 RDD_DISABLE_DFS_CAL,
525 RDD_PULSE_DBG,
526 RDD_READ_PULSE,
527 RDD_RESUME_BF,
528 RDD_IRQ_OFF,
529 };
530
531 static inline int
mt7996_get_rdd_idx(struct mt7996_phy * phy,bool is_background)532 mt7996_get_rdd_idx(struct mt7996_phy *phy, bool is_background)
533 {
534 if (!phy->mt76->cap.has_5ghz)
535 return -1;
536
537 if (is_background)
538 return MT_RDD_IDX_BACKGROUND;
539
540 if (phy->mt76->band_idx == MT_BAND2)
541 return MT_RDD_IDX_BAND2;
542
543 return MT_RDD_IDX_BAND1;
544 }
545
546 static inline struct mt7996_dev *
mt7996_hw_dev(struct ieee80211_hw * hw)547 mt7996_hw_dev(struct ieee80211_hw *hw)
548 {
549 struct mt76_phy *phy = hw->priv;
550
551 return container_of(phy->dev, struct mt7996_dev, mt76);
552 }
553
554 static inline struct mt7996_phy *
__mt7996_phy(struct mt7996_dev * dev,enum mt76_band_id band)555 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)
556 {
557 struct mt76_phy *phy = dev->mt76.phys[band];
558
559 if (!phy)
560 return NULL;
561
562 return phy->priv;
563 }
564
565 static inline struct mt7996_phy *
mt7996_phy2(struct mt7996_dev * dev)566 mt7996_phy2(struct mt7996_dev *dev)
567 {
568 return __mt7996_phy(dev, MT_BAND1);
569 }
570
571 static inline struct mt7996_phy *
mt7996_phy3(struct mt7996_dev * dev)572 mt7996_phy3(struct mt7996_dev *dev)
573 {
574 return __mt7996_phy(dev, MT_BAND2);
575 }
576
577 static inline bool
mt7996_band_valid(struct mt7996_dev * dev,u8 band)578 mt7996_band_valid(struct mt7996_dev *dev, u8 band)
579 {
580 if (!is_mt7996(&dev->mt76))
581 return band <= MT_BAND1;
582
583 return band <= MT_BAND2;
584 }
585
586 static inline struct mt7996_phy *
mt7996_band_phy(struct mt7996_dev * dev,enum nl80211_band band)587 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band)
588 {
589 struct mt76_phy *mphy;
590
591 mphy = dev->mt76.band_phys[band];
592 if (!mphy)
593 return NULL;
594
595 return mphy->priv;
596 }
597
598 static inline struct mt7996_vif_link *
mt7996_vif_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,int link_id)599 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id)
600 {
601 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id);
602 }
603
604 static inline struct mt7996_phy *
mt7996_vif_link_phy(struct mt7996_vif_link * link)605 mt7996_vif_link_phy(struct mt7996_vif_link *link)
606 {
607 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76);
608
609 if (!mphy)
610 return NULL;
611
612 return mphy->priv;
613 }
614
615 static inline struct mt7996_vif_link *
mt7996_vif_conf_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)616 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif,
617 struct ieee80211_bss_conf *link_conf)
618 {
619 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif,
620 link_conf);
621 }
622
623 #define mt7996_for_each_phy(dev, phy) \
624 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \
625 if (((phy) = (dev)->radio_phy[__i]) != NULL)
626
627 extern const struct ieee80211_ops mt7996_ops;
628 extern struct pci_driver mt7996_pci_driver;
629 extern struct pci_driver mt7996_hif_driver;
630
631 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
632 void __iomem *mem_base, u32 device_id);
633 void mt7996_rro_hw_init(struct mt7996_dev *dev);
634 void mt7996_wfsys_reset(struct mt7996_dev *dev);
635 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);
636 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link);
637 int mt7996_register_device(struct mt7996_dev *dev);
638 void mt7996_unregister_device(struct mt7996_dev *dev);
639 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif,
640 struct ieee80211_bss_conf *link_conf,
641 struct mt76_vif_link *mlink);
642 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif,
643 struct ieee80211_bss_conf *link_conf,
644 struct mt76_vif_link *mlink);
645 int mt7996_eeprom_init(struct mt7996_dev *dev);
646 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);
647 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,
648 struct ieee80211_channel *chan);
649 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);
650 bool mt7996_eeprom_has_background_radar(struct mt7996_dev *dev);
651 int mt7996_dma_init(struct mt7996_dev *dev);
652 void mt7996_dma_reset(struct mt7996_dev *dev, bool force);
653 void mt7996_dma_prefetch(struct mt7996_dev *dev);
654 void mt7996_dma_cleanup(struct mt7996_dev *dev);
655 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset);
656 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx,
657 int n_desc, int ring_base, struct mtk_wed_device *wed);
658 void mt7996_init_txpower(struct mt7996_phy *phy);
659 int mt7996_txbf_init(struct mt7996_dev *dev);
660 void mt7996_reset(struct mt7996_dev *dev);
661 int mt7996_run(struct mt7996_phy *phy);
662 int mt7996_mcu_init(struct mt7996_dev *dev);
663 int mt7996_mcu_init_firmware(struct mt7996_dev *dev);
664 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,
665 struct mt7996_vif_link *link,
666 struct mt7996_twt_flow *flow,
667 int cmd);
668 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
669 struct ieee80211_bss_conf *link_conf,
670 struct mt76_vif_link *mlink, bool enable);
671 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
672 struct ieee80211_bss_conf *link_conf,
673 struct mt76_vif_link *mlink,
674 struct mt7996_sta_link *msta_link, int enable);
675 int mt7996_mcu_add_sta(struct mt7996_dev *dev,
676 struct ieee80211_bss_conf *link_conf,
677 struct ieee80211_link_sta *link_sta,
678 struct mt7996_vif_link *link,
679 struct mt7996_sta_link *msta_link,
680 int conn_state, bool newly);
681 int mt7996_mcu_teardown_mld_sta(struct mt7996_dev *dev,
682 struct mt7996_vif_link *link,
683 struct mt7996_sta_link *msta_link);
684 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,
685 struct ieee80211_ampdu_params *params,
686 struct ieee80211_vif *vif, bool enable);
687 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,
688 struct ieee80211_ampdu_params *params,
689 struct ieee80211_vif *vif, bool enable);
690 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev,
691 struct mt76_vif_link *mlink,
692 struct cfg80211_he_bss_color *he_bss_color);
693 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
694 struct ieee80211_bss_conf *link_conf, bool enabled);
695 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
696 struct ieee80211_bss_conf *link_conf,
697 struct mt7996_vif_link *link, u32 changed);
698 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy,
699 struct mt7996_vif_link *link,
700 struct ieee80211_he_obss_pd *he_obss_pd);
701 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct mt7996_sta *msta,
702 struct ieee80211_vif *vif, u8 link_id,
703 bool changed);
704 int mt7996_set_channel(struct mt76_phy *mphy);
705 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);
706 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif,
707 struct ieee80211_bss_conf *link_conf);
708 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,
709 void *data, u16 version);
710 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct mt7996_sta *msta,
711 void *data, u8 link_id, u32 field);
712 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);
713 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len);
714 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num);
715 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);
716 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);
717 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);
718 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);
719 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,
720 const struct mt7996_dfs_pulse *pulse);
721 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,
722 const struct mt7996_dfs_pattern *pattern);
723 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);
724 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);
725 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif,
726 struct ieee80211_bss_conf *link_conf);
727 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);
728 int mt7996_mcu_get_temperature(struct mt7996_phy *phy);
729 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state);
730 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable);
731 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy);
732 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 rdd_idx, u8 val);
733 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,
734 struct cfg80211_chan_def *chandef);
735 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,
736 u16 rate_idx, bool beacon);
737 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
738 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
739 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
740 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
741 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
742 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
743 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);
744 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);
745 void mt7996_mcu_exit(struct mt7996_dev *dev);
746 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag);
747 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id);
748 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled);
749
mt7996_has_hwrro(struct mt7996_dev * dev)750 static inline bool mt7996_has_hwrro(struct mt7996_dev *dev)
751 {
752 return dev->mt76.hwrro_mode != MT76_HWRRO_OFF;
753 }
754
mt7996_max_interface_num(struct mt7996_dev * dev)755 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)
756 {
757 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) +
758 mt7996_band_valid(dev, MT_BAND2)),
759 MT7996_WTBL_BMC_SIZE);
760 }
761
mt7996_wtbl_size(struct mt7996_dev * dev)762 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)
763 {
764 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE;
765 }
766
767 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
768 u32 clear, u32 set);
769
mt7996_irq_enable(struct mt7996_dev * dev,u32 mask)770 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)
771 {
772 if (dev->hif2)
773 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);
774 else
775 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
776
777 tasklet_schedule(&dev->mt76.irq_tasklet);
778 }
779
mt7996_irq_disable(struct mt7996_dev * dev,u32 mask)780 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)
781 {
782 if (dev->hif2)
783 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);
784 else
785 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
786 }
787
788 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
789 size_t len);
790
mt7996_rx_chainmask(struct mt7996_phy * phy)791 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy)
792 {
793 int max_nss = hweight16(phy->orig_antenna_mask);
794 int cur_nss = hweight8(phy->mt76->antenna_mask);
795 u16 tx_chainmask = phy->mt76->chainmask;
796
797 if (cur_nss != max_nss)
798 return tx_chainmask;
799
800 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx);
801 }
802
mt7996_has_wa(struct mt7996_dev * dev)803 static inline bool mt7996_has_wa(struct mt7996_dev *dev)
804 {
805 return !is_mt7990(&dev->mt76);
806 }
807
808 void mt7996_mac_init(struct mt7996_dev *dev);
809 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);
810 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);
811 void mt7996_mac_reset_counters(struct mt7996_phy *phy);
812 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);
813 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
814 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
815 struct sk_buff *skb, struct mt76_wcid *wcid,
816 struct ieee80211_key_conf *key, int pid,
817 enum mt76_txq_id qid, u32 changed);
818 void mt7996_mac_update_beacons(struct mt7996_phy *phy);
819 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
820 void mt7996_mac_work(struct work_struct *work);
821 void mt7996_mac_reset_work(struct work_struct *work);
822 void mt7996_mac_dump_work(struct work_struct *work);
823 void mt7996_mac_sta_rc_work(struct work_struct *work);
824 void mt7996_mac_update_stats(struct mt7996_phy *phy);
825 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,
826 struct mt7996_vif_link *link,
827 struct mt7996_sta_link *msta_link,
828 u8 flowid);
829 void mt7996_mac_sta_deinit_link(struct mt7996_dev *dev,
830 struct mt7996_sta_link *msta_link);
831 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,
832 struct ieee80211_sta *sta,
833 struct ieee80211_twt_setup *twt);
834 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
835 enum mt76_txq_id qid, struct mt76_wcid *wcid,
836 struct ieee80211_sta *sta,
837 struct mt76_tx_info *tx_info);
838 void mt7996_tx_token_put(struct mt7996_dev *dev);
839 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
840 struct sk_buff *skb, u32 *info);
841 void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev);
842 int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q,
843 dma_addr_t dma_addr, void *data);
844 void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data);
845 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);
846 void mt7996_stats_work(struct work_struct *work);
847 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);
848 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);
849 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);
850 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);
851 void mt7996_update_channel(struct mt76_phy *mphy);
852 int mt7996_init_debugfs(struct mt7996_dev *dev);
853 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);
854 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);
855 int mt7996_mcu_add_key(struct mt76_dev *dev, struct mt7996_vif_link *link,
856 struct ieee80211_key_conf *key, int mcu_cmd,
857 struct mt76_wcid *wcid, enum set_key_cmd cmd);
858 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev,
859 struct mt7996_vif_link *link,
860 struct mt7996_sta_link *msta_link,
861 struct ieee80211_key_conf *key);
862 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,
863 struct ieee80211_vif *vif,
864 struct mt7996_vif_link *link,
865 struct mt7996_sta_link *msta_link);
866 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode);
867 #ifdef CONFIG_MAC80211_DEBUGFS
868 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
869 struct ieee80211_sta *sta, struct dentry *dir);
870 void mt7996_link_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
871 struct ieee80211_link_sta *link_sta,
872 struct dentry *dir);
873 #endif
874 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
875 bool hif2, int *irq);
876 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
877
878 #ifdef CONFIG_MTK_DEBUG
879 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir);
880 #endif
881
882 int mt7996_dma_rro_init(struct mt7996_dev *dev);
883
884 #ifdef CONFIG_MT7996_NPU
885 int mt7996_npu_hw_init(struct mt7996_dev *dev);
886 int mt7996_npu_hw_stop(struct mt7996_dev *dev);
887 int mt7996_npu_rx_queues_init(struct mt7996_dev *dev);
888 #else
mt7996_npu_hw_init(struct mt7996_dev * dev)889 static inline int mt7996_npu_hw_init(struct mt7996_dev *dev)
890 {
891 return 0;
892 }
893
mt7996_npu_hw_stop(struct mt7996_dev * dev)894 static inline int mt7996_npu_hw_stop(struct mt7996_dev *dev)
895 {
896 return 0;
897 }
898
mt7996_npu_rx_queues_init(struct mt7996_dev * dev)899 static inline int mt7996_npu_rx_queues_init(struct mt7996_dev *dev)
900 {
901 return 0;
902 }
903 #endif /* CONFIG_MT7996_NPU */
904
905 #endif
906