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Searched refs:MRI (Results 1 – 25 of 658) sorted by relevance

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/src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.h41 MachineRegisterInfo &MRI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
59 bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
61 bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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H A DAMDGPURegisterBankInfo.cpp102 MachineRegisterInfo &MRI; member in __anonb1a32b930111::ApplyRegBankMapping
109 : B(B), RBI(RBI_), MRI(MRI_), NewBank(RB) { in ApplyRegBankMapping()
131 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
134 assert(MRI.getType(SrcReg) == LLT::scalar(1)); in applyBank()
135 assert(MRI.getType(DstReg) == S32); in applyBank()
145 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
146 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
150 assert(!MRI.getRegClassOrRegBank(DstReg)); in applyBank()
151 MRI.setRegBank(DstReg, *NewBank); in applyBank()
158 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
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H A DGCNRegPressure.cpp39 const MachineRegisterInfo &MRI) { in getRegKind() argument
41 const auto RC = MRI.getRegClass(Reg); in getRegKind()
42 auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo()); in getRegKind()
53 const MachineRegisterInfo &MRI) { in inc() argument
64 switch (auto Kind = getRegKind(Reg, MRI)) { in inc()
81 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo(); in inc()
83 Sign * TRI->getRegClassWeight(MRI.getRegClass(Reg)).RegWeight; in inc()
246 const MachineRegisterInfo &MRI) { in getDefRegMask() argument
253 MRI.getMaxLaneMaskForVReg(MO.getReg()) : in getDefRegMask()
254 MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg()); in getDefRegMask()
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H A DAMDGPUCombinerHelper.cpp71 const MachineRegisterInfo &MRI) { in opMustUseVOP3Encoding() argument
73 MRI.getType(MI.getOperand(0).getReg()).getScalarSizeInBits() == 64; in opMustUseVOP3Encoding()
117 static bool allUsesHaveSourceMods(MachineInstr &MI, MachineRegisterInfo &MRI, in allUsesHaveSourceMods() argument
126 for (const MachineInstr &Use : MRI.use_nodbg_instructions(Dst)) { in allUsesHaveSourceMods()
130 if (!opMustUseVOP3Encoding(Use, MRI)) { in allUsesHaveSourceMods()
156 MachineRegisterInfo &MRI) { in isConstantCostlierToNegate() argument
158 if (mi_match(Reg, MRI, m_GFCstOrSplat(FPValReg))) { in isConstantCostlierToNegate()
195 MatchInfo = MRI.getVRegDef(Src); in matchFoldableFneg()
201 if (MRI.hasOneNonDBGUse(Src)) { in matchFoldableFneg()
202 if (allUsesHaveSourceMods(MI, MRI, 0)) in matchFoldableFneg()
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H A DAMDGPUInstructionSelector.cpp64 MRI = &MF.getRegInfo(); in setupMF()
78 const MachineRegisterInfo &MRI) const { in isVCC()
83 auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg); in isVCC()
87 const LLT Ty = MRI.getType(Reg); in isVCC()
91 return MRI.getVRegDef(Reg)->getOpcode() != AMDGPU::G_TRUNC && in isVCC()
109 if (MRI->getType(Dst.getReg()) == LLT::scalar(1)) in constrainCopyLikeIntrin()
113 = TRI.getConstrainedRegClassForOperand(Dst, *MRI); in constrainCopyLikeIntrin()
115 = TRI.getConstrainedRegClassForOperand(Src, *MRI); in constrainCopyLikeIntrin()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
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/src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h94 Register constrainRegToClass(MachineRegisterInfo &MRI,
109 MachineRegisterInfo &MRI,
128 MachineRegisterInfo &MRI,
150 bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
154 bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
175 const MachineRegisterInfo &MRI);
179 const MachineRegisterInfo &MRI);
192 const MachineRegisterInfo &MRI,
198 Register VReg, const MachineRegisterInfo &MRI,
210 const MachineRegisterInfo &MRI,
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H A DMIPatternMatch.h25 [[nodiscard]] bool mi_match(Reg R, const MachineRegisterInfo &MRI, in mi_match() argument
27 return P.match(MRI, R); in mi_match()
31 [[nodiscard]] bool mi_match(MachineInstr &MI, const MachineRegisterInfo &MRI, in mi_match() argument
33 return P.match(MRI, &MI); in mi_match()
41 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
42 return MRI.hasOneUse(Reg) && SubPat.match(MRI, Reg); in match()
55 bool match(const MachineRegisterInfo &MRI, Register Reg) { in match()
56 return MRI.hasOneNonDBGUse(Reg) && SubPat.match(MRI, Reg); in match()
71 const MachineRegisterInfo &MRI) { in matchConstant() argument
72 return getIConstantVRegVal(Reg, MRI); in matchConstant()
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H A DLegalizationArtifactCombiner.h37 MachineRegisterInfo &MRI; variable
54 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI,
57 : Builder(B), MRI(MRI), LI(LI), KB(KB) {} in Builder()
72 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { in tryCombineAnyExt()
74 if (MRI.getType(DstReg) == MRI.getType(TruncSrc)) in tryCombineAnyExt()
75 replaceRegOrBuildCopy(DstReg, TruncSrc, MRI, Builder, UpdatedDefs, in tryCombineAnyExt()
80 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt()
87 if (mi_match(SrcReg, MRI, in tryCombineAnyExt()
98 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt()
100 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
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/src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp52 MachineRegisterInfo &MRI) { in IsRegInClass()
54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
62 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSReg()
63 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); in IsVSReg()
66 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVRReg()
67 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); in IsVRReg()
70 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { in IsF8Reg()
71 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); in IsF8Reg()
74 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { in IsVSFReg()
75 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); in IsVSFReg()
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/src/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperVectorOps.cpp40 LLT DstTy = MRI.getType(Dst); in matchExtractVectorElement()
41 LLT VectorTy = MRI.getType(Vector); in matchExtractVectorElement()
73 getIConstantVRegValWithLookThrough(Index, MRI); in matchExtractVectorElement()
93 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithDifferentIndices()
115 getIConstantVRegValWithLookThrough(Index, MRI); in matchExtractVectorElementWithDifferentIndices()
126 getOpcodeDef<GInsertVectorElement>(Vector, MRI); in matchExtractVectorElementWithDifferentIndices()
133 getIConstantVRegValWithLookThrough(Insert->getIndexReg(), MRI); in matchExtractVectorElementWithDifferentIndices()
150 MachineInstr *Root = getDefIgnoringCopies(MO.getReg(), MRI); in matchExtractVectorElementWithBuildVector()
176 GBuildVector *Build = getOpcodeDef<GBuildVector>(Vector, MRI); in matchExtractVectorElementWithBuildVector()
180 LLT VectorTy = MRI.getType(Vector); in matchExtractVectorElementWithBuildVector()
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H A DUtils.cpp46 Register llvm::constrainRegToClass(MachineRegisterInfo &MRI, in constrainRegToClass() argument
50 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) in constrainRegToClass()
51 return MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
58 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
69 auto *OldRegClass = MRI.getRegClassOrNull(Reg); in constrainOperandRegClass()
70 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass); in constrainOperandRegClass()
95 } else if (OldRegClass != MRI.getRegClassOrNull(Reg)) { in constrainOperandRegClass()
98 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass()
101 Observer->changingAllUsesOfReg(MRI, Reg); in constrainOperandRegClass()
110 MachineRegisterInfo &MRI, const TargetInstrInfo &TII, in constrainOperandRegClass() argument
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H A DCombinerHelper.cpp60 : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer), KB(KB), in CombinerHelper()
83 auto &MRI = *MIB.getMRI(); in buildLogBase2() local
84 LLT Ty = MRI.getType(V); in buildLogBase2()
164 void CombinerHelper::replaceRegWith(MachineRegisterInfo &MRI, Register FromReg, in replaceRegWith() argument
166 Observer.changingAllUsesOfReg(MRI, FromReg); in replaceRegWith()
168 if (MRI.constrainRegAttrs(ToReg, FromReg)) in replaceRegWith()
169 MRI.replaceRegWith(FromReg, ToReg); in replaceRegWith()
176 void CombinerHelper::replaceRegOpWith(MachineRegisterInfo &MRI, in replaceRegOpWith() argument
197 return RBI->getRegBank(Reg, MRI, *TRI); in getRegBank()
202 MRI.setRegBank(Reg, *RegBank); in setRegBank()
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/src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp66 MachineRegisterInfo *MRI; member in __anonb772b8d10111::AArch64AdvSIMDScalar
105 const MachineRegisterInfo *MRI) { in isGPR64() argument
109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()
114 const MachineRegisterInfo *MRI) { in isFPR64() argument
116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && in isFPR64()
118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && in isFPR64()
128 const MachineRegisterInfo *MRI, in getSrcFromCopy() argument
145 MRI) && in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
149 MRI) && in getSrcFromCopy()
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H A DAArch64Combine.td17 [{ return matchFConstantToConstant(*${root}, MRI); }]),
24 [{ return matchICmpRedundantTrunc(*${root}, MRI, Helper.getKnownBits(), ${matchinfo}); }]),
25 (apply [{ applyICmpRedundantTrunc(*${root}, MRI, B, Observer, ${matchinfo}); }])>;
32 [{ return matchFoldGlobalOffset(*${root}, MRI, ${matchinfo}); }]),
33 (apply [{ applyFoldGlobalOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
42 [{ return matchExtAddvToUdotAddv(*${root}, MRI, STI, ${matchinfo}); }]),
43 (apply [{ applyExtAddvToUdotAddv(*${root}, MRI, B, Observer, STI, ${matchinfo}); }])
51 [{ return matchExtUaddvToUaddlv(*${root}, MRI, ${matchinfo}); }]),
52 (apply [{ applyExtUaddvToUaddlv(*${root}, MRI, B, Observer, ${matchinfo}); }])
60 …[{ return matchPushAddSubExt(*${root}, MRI, ${dst}.getReg(), ${src1}.getReg(), ${src2}.getReg()); …
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/src/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp78 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
80 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
82 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
84 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
86 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
96 bool selectUAddSub(MachineInstr &I, MachineRegisterInfo &MRI,
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H A DX86RegisterBankInfo.cpp75 static bool isFPIntrinsic(const MachineRegisterInfo &MRI, in isFPIntrinsic() argument
96 const MachineRegisterInfo &MRI, in hasFPConstraints() argument
100 if (Op == TargetOpcode::G_INTRINSIC && isFPIntrinsic(MRI, MI)) in hasFPConstraints()
114 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
129 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
134 const MachineRegisterInfo &MRI, in onlyUsesFP() argument
149 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyUsesFP()
153 const MachineRegisterInfo &MRI, in onlyDefinesFP() argument
163 return hasFPConstraints(MI, MRI, TRI, Depth); in onlyDefinesFP()
223 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, in getInstrPartialMappingIdxs() argument
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/src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp157 bool matchREV(MachineInstr &MI, MachineRegisterInfo &MRI, in matchREV() argument
163 LLT Ty = MRI.getType(Dst); in matchREV()
193 bool matchTRN(MachineInstr &MI, MachineRegisterInfo &MRI, in matchTRN() argument
199 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchTRN()
214 bool matchUZP(MachineInstr &MI, MachineRegisterInfo &MRI, in matchUZP() argument
220 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchUZP()
230 bool matchZip(MachineInstr &MI, MachineRegisterInfo &MRI, in matchZip() argument
236 unsigned NumElts = MRI.getType(Dst).getNumElements(); in matchZip()
248 MachineRegisterInfo &MRI, in matchDupFromInsertVectorElt() argument
269 MI.getOperand(1).getReg(), MRI); in matchDupFromInsertVectorElt()
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H A DAArch64PostLegalizerCombiner.cpp67 MachineInstr &MI, MachineRegisterInfo &MRI, in matchExtractVecEltPairwiseAdd() argument
71 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in matchExtractVecEltPairwiseAdd()
73 auto Cst = getIConstantVRegValWithLookThrough(Src2, MRI); in matchExtractVecEltPairwiseAdd()
79 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
91 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
92 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd()
94 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
95 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd()
100 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd()
110 MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, in applyExtractVecEltPairwiseAdd() argument
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H A DAArch64PreLegalizerCombiner.cpp50 bool matchFConstantToConstant(MachineInstr &MI, MachineRegisterInfo &MRI) { in matchFConstantToConstant() argument
53 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits(); in matchFConstantToConstant()
60 return all_of(MRI.use_nodbg_instructions(DstReg), in matchFConstantToConstant()
76 bool matchICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in matchICmpRedundantTrunc() argument
85 LLT LHSTy = MRI.getType(LHS); in matchICmpRedundantTrunc()
92 if (!mi_match(LHS, MRI, m_GTrunc(m_Reg(WideReg))) || in matchICmpRedundantTrunc()
93 !mi_match(RHS, MRI, m_SpecificICst(0))) in matchICmpRedundantTrunc()
96 LLT WideTy = MRI.getType(WideReg); in matchICmpRedundantTrunc()
105 void applyICmpRedundantTrunc(MachineInstr &MI, MachineRegisterInfo &MRI, in applyICmpRedundantTrunc() argument
110 LLT WideTy = MRI.getType(WideReg); in applyICmpRedundantTrunc()
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H A DAArch64InstructionSelector.cpp114 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI);
118 MachineRegisterInfo &MRI);
120 bool convertPtrAddToAdd(MachineInstr &I, MachineRegisterInfo &MRI);
123 MachineRegisterInfo &MRI) const;
125 MachineRegisterInfo &MRI) const;
141 MachineRegisterInfo &MRI);
143 bool selectVectorAshrLshr(MachineInstr &I, MachineRegisterInfo &MRI);
144 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI);
157 MachineRegisterInfo &MRI) const;
177 MachineRegisterInfo &MRI);
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H A DAArch64RegisterBankInfo.cpp303 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getInstrAlternativeMappings() local
309 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
330 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
370 TypeSize Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
408 MachineRegisterInfo &MRI = OpdMapper.getMRI(); in applyMappingImpl() local
423 MRI.setRegBank(Ext.getReg(0), getRegBank(AArch64::GPRRegBankID)); in applyMappingImpl()
437 const MachineRegisterInfo &MRI = MF.getRegInfo(); in getSameKindOfOperandsMapping() local
443 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameKindOfOperandsMapping()
459 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg()); in getSameKindOfOperandsMapping()
476 static bool isFPIntrinsic(const MachineRegisterInfo &MRI, in isFPIntrinsic() argument
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/src/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp65 void processCandidate(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
68 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
71 void processInst(MachineRegisterInfo *MRI, MachineInstr *Inst,
73 void checkADDrr(MachineRegisterInfo *MRI, MachineOperand *RelocOp,
75 void checkShift(MachineRegisterInfo *MRI, MachineBasicBlock &MBB,
128 void BPFMISimplifyPatchable::checkADDrr(MachineRegisterInfo *MRI, in checkADDrr() argument
138 llvm::make_early_inc_range(MRI->use_operands(Op0.getReg()))) { in checkADDrr()
140 if (!MRI->getUniqueVRegDef(MO.getReg())) in checkADDrr()
176 void BPFMISimplifyPatchable::checkShift(MachineRegisterInfo *MRI, in checkShift() argument
190 void BPFMISimplifyPatchable::processCandidate(MachineRegisterInfo *MRI, in processCandidate() argument
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/src/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp46 MachineRegisterInfo &MRI = MF.getRegInfo(); in addConstantsToTrack() local
69 auto *BuildVec = MRI.getVRegDef(SrcReg); in addConstantsToTrack()
87 MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); in addConstantsToTrack()
105 MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg()); in addConstantsToTrack()
116 auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg()); in addConstantsToTrack()
117 if (!MRI.getRegClassOrNull(Reg) && RC) in addConstantsToTrack()
118 MRI.setRegClass(Reg, RC); in addConstantsToTrack()
119 MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg); in addConstantsToTrack()
130 MachineRegisterInfo &MRI = MF.getRegInfo(); in foldConstantsIntoIntrinsics() local
139 MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg()); in foldConstantsIntoIntrinsics()
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/src/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp52 bool isRegInGprb(Register Reg, MachineRegisterInfo &MRI) const;
53 bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const;
62 MachineRegisterInfo &MRI);
65 MachineRegisterInfo &MRI);
68 bool selectCopy(MachineInstr &MI, MachineRegisterInfo &MRI) const;
70 MachineRegisterInfo &MRI) const;
73 MachineRegisterInfo &MRI, bool IsLocal = true,
77 MachineRegisterInfo &MRI) const;
79 MachineRegisterInfo &MRI) const;
83 MachineRegisterInfo &MRI) const;
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/src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
188 MachineRegisterInfo &MRI, in guessRegClass() argument
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
194 const unsigned Size = MRI.getType(Reg).getSizeInBits(); in guessRegClass()
214 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, in selectCopy() argument
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI); in selectCopy()
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